In this paper, we analyze the best relay selection scheme for the soft-decision-and-forward (SDF) cooperative networks with multiple relays. The term `best relay selection' implies that the relay having the largest end-to-end signal-to-noise ratio is selected to transmit in the second phase transmission. The approximate performances in terms of pairwise error probability (PEP) and bit error rate (BER) are analyzed and compared with the conventional multiple-relay transmission scheme where all the relays participate in the second phase transmission. Using the asymptotics of the Fox's H-function, the diversity orders of the best relay selection and conventional relay scheme for the SDF cooperative networks are derived. It is shown that both have the same full diversity order. The numerical results show that the best relay selection scheme outperforms the conventional one in terms of bit error rate.

3D Mesh segmentation has become an important research field in computer graphics during the past few decades. Many geometry based and semantic oriented approaches for 3D mesh segmentation has been presented. However, only a few algorithms based on Markov Random Field (MRF) has been presented for 3D object segmentation. In this letter, we present a definition of mesh segmentation according to the labeling problem. Inspired by the capability of MRF combining the geometric information and the topology information of a 3D mesh, we propose a novel 3D mesh segmentation model based on MRF and Graph Cuts. Experimental results show that our MRF-based schema achieves an effective segmentation.

In this letter, dynamic decode-and-forward (DDF) protocol and static decode-and-forward (SDF) protocol are considered in a two-way half-duplex fading system, where two sources are equipped with multiple antennas and a relay is equipped with a single antenna. Their closed-form expressions of diversity multiplexing tradeoff (DMT) are derived, respectively. From the results, DDF always outperforms SDF in terms of DMT, achieves DMT gain over nonorthogonal amplify-and-forward (NAF) in low spectral efficiency scenarios, but is inferior to NAF in high spectral efficiency scenarios.

In this paper, the performance of the soft-decision-and-forward (SDF) protocol in the cooperative communication network with one source, one relay, and one destination, where each node has two transmit and receive antennas, is analyzed in terms of the bit error rate (BER) obtained from the pairwise error probability (PEP). Using the moment generating function and Q-function approximation, the PEP of SDF protocol is calculated and we confirm that the SDF with two antennas achieves the full diversity order. For the slow-varying Rayleigh fading channel, the optimal power allocation ratio can be determined so as to minimize the average PEP (or BER). Due to the difficulty of deriving the optimal value analytically, an alternative strategy of maximizing the product signal-to-noise ratio (SNR) of direct and relay links, which we call the suboptimal power allocation, is considered. Through a numerical analysis, we show that the performance gap between the suboptimal and optimal power allocation strategies is negligible in the high SNR region.

In orthogonal frequency division multiplexing (OFDM) the multipath exceeding the guard interval (GI) causes inter-symbol interference (ISI) and inter-carrier interference (ICI), thereby making it difficult to achieve high data rate transmission. In this paper, the double window cancellation and combining (DWCC), introduced in [14], is analyzed by investigating SINR distribution under different delay spread channels. The analysis indicates that the extension of processing window in iterative cancellation can have an adverse effect on the performance for small interference levels. In addition, the optimal combining of DWCC and turbo equalization (TE), named TE-DWCC, is investigated by varying the iterative cancellation procedure between DWCC and channel decoder and the decision feedback type such as hard decision feedback (HDF) or soft decision feedback (SDF). Finally, by changing interference level, code rate, and decision feedback type, the performance of TE-DWCC is compared with the conventional canceller that adopts turbo equalization in the exponentially distributed slow fading channel.

This paper presents a novel high-speed, low-complexity two-parallel 128-point radix-24 FFT/IFFT processor for MB-OFDM ultrawideband (UWB) systems. The proposed high-speed, low-complexity FFT architecture can provide a higher throughput rate and low hardware complexity by using a two-parallel data-path scheme and a single-path delay-feedback (SDF) structure. The radix-24 FFT algorithm is also realized in our processor to reduce the number of complex multiplications. The proposed FFT/IFFT processor has been designed and implemented with 0.18-µm CMOS technology in a supply voltage of 1.8 V. The proposed two-parallel FFT/IFFT processor has a throughput rate of up to 900 Msample/s at 450 MHz while requiring much smaller hardware complexity and low power consumption.

This paper proposes the new radix-24 FFT algorithm and an efficient pipeline FFT architecture based on the algorithm for wideband OFDM systems. The proposed pipeline architecture has the same number of multipliers as that of the radix-22 algorithm. However, the multiplication complexity is reduced more than 30% by using the newly proposed CSD constant multipliers instead of the programmable multipliers. From the synthesis simulations of a standard 0.35 µm CMOS SAMSUNG process, the proposed CSD constant complex multiplier achieved a reduction of more than 60% of the power consumption/area when compared with the conventional programmable complex multiplier.

This paper proposes a new modified radix-24 FFT algorithm and an efficient pipeline FFT architecture based on this algorithm for OFDM systems. This pipeline FFT architecture has the same number of multipliers as that of the radix-22 algorithm. However, the multiplication complexity could be reduced by more than 30% by replacing one half of the programmable multipliers by the newly proposed CSD constant multipliers. From the synthesis simulations of a standard 0.35 µm CMOS SAMSUNG process, a proposed CSD constant complex multiplier achieved more than 60% area efficiency when compared to the conventional programmable complex multiplier. This promoted efficiency could be used to the design of a long length FFT processor in wireless OFDM applications, which needs more power and area efficiency.