New Radix-2 to the 4th Power Pipeline FFT Processor

Jung-Yeol OH; Myoung-Seob LIM

doi:10.1093/ietele/e88-c.8.1740

New Radix-2 to the 4th Power Pipeline FFT Processor

Jung-Yeol OH, Myoung-Seob LIM

Full Text Views

0

Cite this

Summary :

This paper proposes a new modified radix-2⁴ FFT algorithm and an efficient pipeline FFT architecture based on this algorithm for OFDM systems. This pipeline FFT architecture has the same number of multipliers as that of the radix-2² algorithm. However, the multiplication complexity could be reduced by more than 30% by replacing one half of the programmable multipliers by the newly proposed CSD constant multipliers. From the synthesis simulations of a standard 0.35 µm CMOS SAMSUNG process, a proposed CSD constant complex multiplier achieved more than 60% area efficiency when compared to the conventional programmable complex multiplier. This promoted efficiency could be used to the design of a long length FFT processor in wireless OFDM applications, which needs more power and area efficiency.

Publication: IEICE TRANSACTIONS on Electronics Vol.E88-C No.8 pp.1740-1746

Publication Date: 2005/08/01

Publicized

Online ISSN

DOI: 10.1093/ietele/e88-c.8.1740

Type of Manuscript: Special Section PAPER (Special Section on Papers Selected from AP-ASIC 2004)

Category

Cite this

Copy

Jung-Yeol OH, Myoung-Seob LIM, "New Radix-2 to the 4th Power Pipeline FFT Processor" in IEICE TRANSACTIONS on Electronics, vol. E88-C, no. 8, pp. 1740-1746, August 2005, doi: 10.1093/ietele/e88-c.8.1740.
Abstract: This paper proposes a new modified radix-2⁴ FFT algorithm and an efficient pipeline FFT architecture based on this algorithm for OFDM systems. This pipeline FFT architecture has the same number of multipliers as that of the radix-2² algorithm. However, the multiplication complexity could be reduced by more than 30% by replacing one half of the programmable multipliers by the newly proposed CSD constant multipliers. From the synthesis simulations of a standard 0.35 µm CMOS SAMSUNG process, a proposed CSD constant complex multiplier achieved more than 60% area efficiency when compared to the conventional programmable complex multiplier. This promoted efficiency could be used to the design of a long length FFT processor in wireless OFDM applications, which needs more power and area efficiency.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e88-c.8.1740/_p

Copy

@ARTICLE{e88-c_8_1740,
author={Jung-Yeol OH, Myoung-Seob LIM, },
journal={IEICE TRANSACTIONS on Electronics},
title={New Radix-2 to the 4th Power Pipeline FFT Processor},
year={2005},
volume={E88-C},
number={8},
pages={1740-1746},
abstract={This paper proposes a new modified radix-2⁴ FFT algorithm and an efficient pipeline FFT architecture based on this algorithm for OFDM systems. This pipeline FFT architecture has the same number of multipliers as that of the radix-2² algorithm. However, the multiplication complexity could be reduced by more than 30% by replacing one half of the programmable multipliers by the newly proposed CSD constant multipliers. From the synthesis simulations of a standard 0.35 µm CMOS SAMSUNG process, a proposed CSD constant complex multiplier achieved more than 60% area efficiency when compared to the conventional programmable complex multiplier. This promoted efficiency could be used to the design of a long length FFT processor in wireless OFDM applications, which needs more power and area efficiency.},
keywords={},
doi={10.1093/ietele/e88-c.8.1740},
ISSN={},
month={August},}

Copy

TY - JOUR
TI - New Radix-2 to the 4th Power Pipeline FFT Processor
T2 - IEICE TRANSACTIONS on Electronics
SP - 1740
EP - 1746
AU - Jung-Yeol OH
AU - Myoung-Seob LIM
PY - 2005
DO - 10.1093/ietele/e88-c.8.1740
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E88-C
IS - 8
JA - IEICE TRANSACTIONS on Electronics
Y1 - August 2005
AB - This paper proposes a new modified radix-2⁴ FFT algorithm and an efficient pipeline FFT architecture based on this algorithm for OFDM systems. This pipeline FFT architecture has the same number of multipliers as that of the radix-2² algorithm. However, the multiplication complexity could be reduced by more than 30% by replacing one half of the programmable multipliers by the newly proposed CSD constant multipliers. From the synthesis simulations of a standard 0.35 µm CMOS SAMSUNG process, a proposed CSD constant complex multiplier achieved more than 60% area efficiency when compared to the conventional programmable complex multiplier. This promoted efficiency could be used to the design of a long length FFT processor in wireless OFDM applications, which needs more power and area efficiency.
ER -