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[Keyword] CSD(16hit)

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  • Robust Time Synchronization Algorithm for IEEE 802.11ac WLAN Systems

    Soohyun JANG  Jaeyoung ROH  Seongjoo LEE  Yunho JUNG  

     
    LETTER-Communication Theory and Signals

      Vol:
    E98-A No:1
      Page(s):
    441-444

    In this letter, a robust time synchronization algorithm is proposed for MIMO-OFDM based WLAN systems. IEEE 802.11ac MIMO-OFDM WLAN standard specifies that the preamble with cyclic shift diversity (CSD) scheme is used for time and frequency synchronization. However, since the CSD scheme introduces multiple cross-correlation peaks at the receiver, serious performance degradation appears if the conventional cross-correlation based algorithm is applied. In the proposed algorithm, the time synchronization error due to multiple peaks is compensated by adding the cross-correlation value to its reverse cyclic-shifted version. Simulation results show that the proposed algorithm achieves an SNR gain of 1.5 to 4.5dB for the synchronization failure rate of 10-2 compared with the existing algorithms.

  • Fixed-Width Group CSD Multiplier Design

    Yong-Eun KIM  Kyung-Ju CHO  Jin-Gyun CHUNG  Xinming HUANG  

     
    PAPER-Fundamentals of Information Systems

      Vol:
    E93-D No:6
      Page(s):
    1497-1503

    This paper presents an error compensation method for fixed-width group canonic signed digit (GCSD) multipliers that receive a W-bit input and generate a W-bit product. To efficiently compensate for the truncation error, the encoded signals from the GCSD multiplier are used for the generation of the error compensation bias. By Synopsys simulations, it is shown that the proposed method leads to up to 84% reduction in power consumption and up to 78% reduction in area compared with the fixed-width modified Booth multipliers.

  • CSD-Based Programmable Multiplier Design for Predetermined Coefficient Groups

    Yong-Eun KIM  Kyung-Ju CHO  Jin-Gyun CHUNG  Xinming HUANG  

     
    LETTER-VLSI Design Technology and CAD

      Vol:
    E93-A No:1
      Page(s):
    324-326

    An efficient multiplier design method for predetermined coefficient groups is presented based on the variation of canonic signed digit (CSD) encoding and partial product sharing. By applications to radix-24 FFT structure and the pulse-shaping filter design used in CDMA, it is shown that the proposed method significantly reduces the area, propagation delay and power consumption compared with previous methods.

  • A 70 MHz Multiplierless FIR Hilbert Transformer in 0.35 µm Standard CMOS Library

    Yasuhiro TAKAHASHI  Toshikazu SEKINE  Michio YOKOYAMA  

     
    PAPER-VLSI Design Technology and CAD

      Vol:
    E90-A No:7
      Page(s):
    1376-1383

    This paper presents the implementation of a 31-tap FIR Hilbert transform digital filter chip used in the digital-IF receivers, to confirm the effectiveness of our new design method. Our design method that we previously reported is based on a computation sharing multiplier using a new horizontal and vertical common subexpression techniques. A 31-tap FIR Hilbert transform digital filter was implemented and fabricated in 0.35 µm CMOS standard cell library. The chip's core contains approximately 33k transistors and occupies 0.86 mm2. The chip also has an operating speed of 70 MHz over. The implementation results show that the proposed Hilbert transformer has a smallest cost factor and so that is a high performance filter.

  • Fast Fourier Transform Algorithm for Low-Power and Area-Efficient Implementation

    Jung-Yeol OH  Myoung-Seob LIM  

     
    LETTER-Devices/Circuits for Communications

      Vol:
    E89-B No:4
      Page(s):
    1425-1429

    This paper proposes the new radix-24 FFT algorithm and an efficient pipeline FFT architecture based on the algorithm for wideband OFDM systems. The proposed pipeline architecture has the same number of multipliers as that of the radix-22 algorithm. However, the multiplication complexity is reduced more than 30% by using the newly proposed CSD constant multipliers instead of the programmable multipliers. From the synthesis simulations of a standard 0.35 µm CMOS SAMSUNG process, the proposed CSD constant complex multiplier achieved a reduction of more than 60% of the power consumption/area when compared with the conventional programmable complex multiplier.

  • New Radix-2 to the 4th Power Pipeline FFT Processor

    Jung-Yeol OH  Myoung-Seob LIM  

     
    PAPER

      Vol:
    E88-C No:8
      Page(s):
    1740-1746

    This paper proposes a new modified radix-24 FFT algorithm and an efficient pipeline FFT architecture based on this algorithm for OFDM systems. This pipeline FFT architecture has the same number of multipliers as that of the radix-22 algorithm. However, the multiplication complexity could be reduced by more than 30% by replacing one half of the programmable multipliers by the newly proposed CSD constant multipliers. From the synthesis simulations of a standard 0.35 µm CMOS SAMSUNG process, a proposed CSD constant complex multiplier achieved more than 60% area efficiency when compared to the conventional programmable complex multiplier. This promoted efficiency could be used to the design of a long length FFT processor in wireless OFDM applications, which needs more power and area efficiency.

  • A Partial MILP Algorithm for the Design of Linear Phase FIR Filters with SPT Coefficients

    Chia-Yu YAO  Chiang-Ju CHIEN  

     
    PAPER-Digital Signal Processing

      Vol:
    E85-A No:10
      Page(s):
    2302-2310

    This article presents a three-step method for designing linear phase FIR filters with signed-powers-of-two (SPT) coefficients. In Step one, a prototype optimal FIR filter is designed by the Remez exchange algorithm. In Step two, a scaling factor is selected by employing simple ad-hoc rules. In Step three, each coefficient of the prototype filter is scaled by the scaling factor and is quantized coarsely as the canonic-signed-digit (CSD) representation. Then, a mixed-integer-linear-programming (MILP) algorithm is applied to three least significant digits (LSDs) of the filter's coefficients to reduce the number of SPT terms. Design examples demonstrate that the proposed algorithm is able to produce linear phase fixed-point FIR filters using fewer SPT terms than the existing methods under the same normalized peak ripple magnitude (NPRM) specification.

  • Parallel Evolutionary Design of Constant-Coefficient Multipliers

    Dingjun CHEN  Takafumi AOKI  Naofumi HOMMA  Tatsuo HIGUCHI  

     
    LETTER-VLSI Design Technology and CAD

      Vol:
    E85-A No:2
      Page(s):
    508-512

    We introduce PC Linux cluster computing techniques to an Evolutionary Graph Generation (EGG) system, and successfully implement the parallel version of the EGG system, called PEGG. Our survey satisfactorily shows that the parallel evolutionary approach meets our expectation that the final solutions obtained from PEGG will be as good as or better than those obtained from EGG, and that PEGG can ultimately improve the speed of evolution.

  • Design of FIR Digital Filters with CSD Coefficients Having Power-of-Two DC Gain and Their FPGA Implementation for Minimum Critical Path

    Mitsuru YAMADA  Akinori NISHIHARA  

     
    PAPER-Digital Signal Processing

      Vol:
    E84-A No:8
      Page(s):
    1997-2003

    For low-complexity linear-phase FIR digital filters which have coefficients expressed as canonic signed digit (CSD) code, a design method to impose power-of-two DC gain is proposed. Output signal level can easily be compensated to that of input so that cascading many stages do not cause any gain errors, which are harmful in, for example, high precision measurement systems. The design is formulated as an optimization problem with magnitude response constraints. The integer linear programming modified for CSD codes is solved by the branch and bound method. The design example shows the effectiveness of the obtained filter in comparison with existing CSD filters. Also, an evaluation method for the area to implement the filter into field programmable gate array (FPGA) is proposed. The implementation example shows that the minimum critical path is obtained with only a little increase in the die area.

  • Neighboring Full-Search Algorithm for Multiplierless FIR Filter Design

    Chung J. KUO  Hung C. CHIEN  Woei H. LIN  

     
    LETTER-Digital Signal Processing

      Vol:
    E83-A No:11
      Page(s):
    2379-2381

    The canonic signed digit code used to represent the coefficients of power-of-two FIR (2PFIR) filter is nonuniformly distributed in the coefficient space. This paper proposed a neighboring full-search algorithm to design the multiplierless FIR filter such that this nonuniform distribution characteristics is exploited. The proposed procedure can provide a multiplierless FIR filter with fewer numbers of nonzero digits compared with others due to the joint consideration in finding and quantizing the FIR filter coefficients and the exhaustive search nature of the proposed algorithm.

  • Flexible Resource Allocation Scheme for GSM Data Services

    Jeu-Yih JENG  Yi-Bing LIN  Herman Chung-Hwa RAO  

     
    PAPER-Communication Networks and Services

      Vol:
    E81-B No:10
      Page(s):
    1797-1802

    In GSM High Speed Circuit Switched Data (HSCSD), the data rate can be increased by using multiple time slots instead of single time slot. Multiple time-slot assignment results in high blocking rate. To accommodate more users, flexible resource allocation strategies have been proposed. Since GSM follows TDMA/FDMA, the channels (time slots) in a base station are segmented by frequency carriers. The base station must allocate the channels which belong to the same frequency carrier to individual requests. This Flexible Resource Allocation scheme for GSM (FRA-GSM) is contrastive to the scheme proposed in our previous studies where a base station may arbitrarily allocate idle channels in the base station to incoming requests. We define satisfaction indication SI as the measurement to compare the performance of these schemes. Experiment results indicate that FRA-GSM scheme has good performance when the user mobility is high, or when some cost factors are taken into account.

  • Dynamic Scheduling for GSM Data Services

    Jeu-Yih JENG  Chi-Wai LIN  Yi-Bing LIN  

     
    PAPER-Network and traffic control

      Vol:
    E80-B No:2
      Page(s):
    296-300

    A new GSM data protocol called high speed circuit switched data (HSCSD) have been developed by European Telecommunications Standards Institute (ETSI) for high speed file transfer and mobile video applications. HSCSD increases data rate by using multiple TDMA time slots (up to 8) instead of one time slot in the current GSM implementation. The problem of multiple time slot assignment is that blocking rate of the system will increase. This problem can be solved by flexible resource assignment where the service specifies the maximum and the minimum capacity. Based on the current available capacity of a base station, a user will be assigned any rate between the maximum and the minimum capacities. This article describes HSCSD protocol and presents four radio resource allocation strategies for HSCSD: always allocates maximum, always allocates minimum, allocates maximum unless available resources are not enough, and allocates resources according to the current blocking statistics of the base station. A simulation model is proposed to investigate the performance of these algorithms. The blocking probability, the call completion probability, and the quality of service are used to evaluate the effects of algorithms in different system behaviors.

  • Fast FIR Digital Filter Structures Using Minimal Number of Adders and Its Application to Filter Design

    Mitsuhiko YAGYU  Akinori NISHIHARA  Nobuo FUJII  

     
    PAPER

      Vol:
    E79-A No:8
      Page(s):
    1120-1129

    This paper proposes fast FIR digital filter structures using the minimal number of adders. Filter coefficients are expressed with canonic signed digit (CSD) code and Hartley's technique is used to minimize the number of adders and subtractors. The proposed filters implemented as wired logic are fast because the structure having the shortest critical path is selected. Two algorithms are given to obtain such fast structures. In many examples the critical path length of the filter structures obtained using the proposed method is equal to that of the conventional CSD structures. This paper also presents a new design method of FIR filters using the mixed integer programming (MILP). Utilization of common expressions in Hartley's technique widens the CSD coefficient space. Thus the MILP may lead to better frequency responses. Superior frequency responses are actually obtained in many simulations.

  • Design of FIR Digital Filters Using Estimates of Error Function over CSD Coefficient Space

    Mitsuhiko YAGYU  Akinori NISHIHARA  Nobuo FUJII  

     
    PAPER

      Vol:
    E79-A No:3
      Page(s):
    283-290

    This paper proposes an algorithm for the design of FIR digital filters whose coefficients have CSD representations. The total number of nonzero digits is specified. A set of filters whose frequency responses have less than or equal to a given Chebyshev error have their coefficients in a convex polyhedron in the Euclid space. The proposed algorithm searches points where a coefficient is maximum or minimum in the convex polyhedron by using linear programing. These points are connected whih the origin to make a convex cone. Then the algorithm evaluates CSD points near these edges of the cone. Moving along these edges means the scaling of frequency responses. The point where the frequency response is the best among all the candidates under the condition of specified total number of nonzero digits is selected as the solution. Several techniques are used to reduce the calculation time. Design examples show that the proposed method can design better frequency responses than the conventional methods.

  • Highly Efficient Universal Coding with Classifying to Subdictionaries for Text Compression

    Yasuhiko NAKANO  Hironori YAHAGI  Yoshiyuki OKADA  Shigeru YOSHIDA  

     
    PAPER-Algorithms, Data Structures and Computational Complexity

      Vol:
    E77-A No:9
      Page(s):
    1520-1526

    We developed a simple, practical, adaptive data compression algorithm of the LZ78 class. According to the Lempel-Ziv greedy parsing, a string boundary is not related to the statistical history modeled by finite-state sources. We have already reported an algorithm classifying data into subdictionaries (CSD), which uses multiple subdictionaries and conditions the current string by using the previous one to obtain a higher compression ratio. In this paper, we present a practical implementation of this method suitable for any kinds of data, and show that CSD is more efficient than the LZC which is the method used by the program compress available on UNIX systems. The CSD compression performance was about 10% better than that of LZC with the practical dictionary size, an 8k-entry dictionary when the test data was from the Calgary Compression Corpus. With hashing, the CSD processing speed became as fast as that of LZC, although the CSD algorithm was more complicated than LZC.

  • Standardization of Telemetry Signal Transmission by CCSDS and an Experiment Using a Satellite in a Highly Elliptical Orbit

    Tadashi TAKANO  Takahiro YAMADA  Koshiro SHUTO  Toshiyuki TANAKA  Katherine I. MOYD  

     
    REVIEW PAPER

      Vol:
    E76-B No:5
      Page(s):
    466-472

    The Consultative Committee of Space Data Systems (CCSDS) proposes a packetized telemetry scheme for the convenience of data exchange and networking in space activity. This paper describes the outline of the telemetry scheme and the on-orbit experiment which was carried out to show the applicability of the proposed CCSDS packet telemetry scheme using the Japan's satellite "Hiten" in a highly elliptical orbit. The telemetry data which are generated by the onboard instruments are packetized in Hiten, and reformed to the original data in earth stations successfully. The experimental results show that the standardized scheme is helpful for tracking cross-support between organizations, and that the concatenated code is quite effective to transmit data in a low C/N condition.