A novel 10-Gb/s fast acquisition bit-synchronization circuit for use in a Tb/s throughput optical packet switch has been developed. The circuit is a best-sampled-data-select type based on multiple phase-clocks, and it processes the asynchronous input packets into a synchronous data stream in a serial manner, which is advantageous in terms of circuit scale and consumption power compared with the parallel processing type. The circuit was developed using Si-bipolar ultrahigh-speed gate arrays and it was used to develop a 10-Gb/s optical asynchronous packet receiver module. The core logic of this circuit module required about 100 gates, consume 6 W, and the size of the module was reduced to only 170 mm (W)
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Copy
Akio TAJIMA, Hiroaki TAKAHASHI, Yoshiharu MAENO, Soichiro ARAKI, Naoya HENMI, "A 10-Gb/s Optical Asynchronous Packet Receiver with a Fast Bit-Synchronization Circuit" in IEICE TRANSACTIONS on Communications,
vol. E82-B, no. 8, pp. 1121-1126, August 1999, doi: .
Abstract: A novel 10-Gb/s fast acquisition bit-synchronization circuit for use in a Tb/s throughput optical packet switch has been developed. The circuit is a best-sampled-data-select type based on multiple phase-clocks, and it processes the asynchronous input packets into a synchronous data stream in a serial manner, which is advantageous in terms of circuit scale and consumption power compared with the parallel processing type. The circuit was developed using Si-bipolar ultrahigh-speed gate arrays and it was used to develop a 10-Gb/s optical asynchronous packet receiver module. The core logic of this circuit module required about 100 gates, consume 6 W, and the size of the module was reduced to only 170 mm (W)
URL: https://global.ieice.org/en_transactions/communications/10.1587/e82-b_8_1121/_p
Copy
@ARTICLE{e82-b_8_1121,
author={Akio TAJIMA, Hiroaki TAKAHASHI, Yoshiharu MAENO, Soichiro ARAKI, Naoya HENMI, },
journal={IEICE TRANSACTIONS on Communications},
title={A 10-Gb/s Optical Asynchronous Packet Receiver with a Fast Bit-Synchronization Circuit},
year={1999},
volume={E82-B},
number={8},
pages={1121-1126},
abstract={A novel 10-Gb/s fast acquisition bit-synchronization circuit for use in a Tb/s throughput optical packet switch has been developed. The circuit is a best-sampled-data-select type based on multiple phase-clocks, and it processes the asynchronous input packets into a synchronous data stream in a serial manner, which is advantageous in terms of circuit scale and consumption power compared with the parallel processing type. The circuit was developed using Si-bipolar ultrahigh-speed gate arrays and it was used to develop a 10-Gb/s optical asynchronous packet receiver module. The core logic of this circuit module required about 100 gates, consume 6 W, and the size of the module was reduced to only 170 mm (W)
keywords={},
doi={},
ISSN={},
month={August},}
Copy
TY - JOUR
TI - A 10-Gb/s Optical Asynchronous Packet Receiver with a Fast Bit-Synchronization Circuit
T2 - IEICE TRANSACTIONS on Communications
SP - 1121
EP - 1126
AU - Akio TAJIMA
AU - Hiroaki TAKAHASHI
AU - Yoshiharu MAENO
AU - Soichiro ARAKI
AU - Naoya HENMI
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Communications
SN -
VL - E82-B
IS - 8
JA - IEICE TRANSACTIONS on Communications
Y1 - August 1999
AB - A novel 10-Gb/s fast acquisition bit-synchronization circuit for use in a Tb/s throughput optical packet switch has been developed. The circuit is a best-sampled-data-select type based on multiple phase-clocks, and it processes the asynchronous input packets into a synchronous data stream in a serial manner, which is advantageous in terms of circuit scale and consumption power compared with the parallel processing type. The circuit was developed using Si-bipolar ultrahigh-speed gate arrays and it was used to develop a 10-Gb/s optical asynchronous packet receiver module. The core logic of this circuit module required about 100 gates, consume 6 W, and the size of the module was reduced to only 170 mm (W)
ER -