A novel 10-Gb/s fast acquisition bit-synchronization circuit for use in a Tb/s throughput optical packet switch has been developed. The circuit is a best-sampled-data-select type based on multiple phase-clocks, and it processes the asynchronous input packets into a synchronous data stream in a serial manner, which is advantageous in terms of circuit scale and consumption power compared with the parallel processing type. The circuit was developed using Si-bipolar ultrahigh-speed gate arrays and it was used to develop a 10-Gb/s optical asynchronous packet receiver module. The core logic of this circuit module required about 100 gates, consume 6 W, and the size of the module was reduced to only 170 mm (W)130 mm (D) 10 mm (H). Using the receiver module, a fast acquisition time of 9 bits and receiver sensitivity penalty of less than 1.5 dB due to re-synchronization were measured.

A novel 10-Gb/s fast acquisition bit-synchronization circuit for use in a Tb/s throughput optical packet switch has been developed. The circuit is a best-sampled-data-select type based on multiple phase-clocks, and it processes the asynchronous input packets into a synchronous data stream in a serial manner, which is advantageous in terms of circuit scale and consumption power compared with the parallel processing type. The circuit was developed using Si-bipolar ultrahigh-speed gate arrays and it was used to develop a 10-Gb/s optical asynchronous packet receiver module. The core logic of this circuit module required about 100 gates, consume 6 W, and the size of the module was reduced to only 170 mm (W)130 mm (D) 10 mm (H). Using the receiver module, a fast acquisition time of 9 bits and receiver sensitivity penalty of less than 1.5 dB due to re-synchronization were measured.

This paper proposes Photonic Core Node based on a 2.56-Terabit/s opto-electronic switching fabric, which can economically handle the rapidly increasing multimedia traffics, such as Internet traffic. We have successfully developed the first prototype of Photonic Core Node. The prototype consists of a single-stage full-crossbar opto-electronic switching fabric, super-packet buffers for input queuing, and a desynchronized-round-robin scheduler. The switching fabric is upgradable up to 2.56 Tb/s, and employs wavelength-division-multiplexing techniques, which dramatically reduce the total number of optical switching elements down to one-eighth the number of those used in a conventional switching fabric. The super-packet buffer assembles 16 ATM cells routed to the same output port into a single fixed-length packet. The super-packet-switching scheme drastically reduces the overhead of optical switching from 32 to 2.9%, although it tends to decrease effective throughput. The desynchronized-round-robin scheduler maintains nearly 100% effective throughput for random traffic, recursively resolving the contention of connection requests in one scheduling routine while keeping fairness in a round robin manner. The proposed Photonic Core Node can accommodate not only ATM switching but also WDM optical path grooming/multiplexing, and IP routing by using IP input buffer interfaces, because optical switches are bit-rate/format-independent.

This paper proposes Photonic Core Node based on a 2.56-Terabit/s opto-electronic switching fabric, which can economically handle the rapidly increasing multimedia traffics, such as Internet traffic. We have successfully developed the first prototype of Photonic Core Node. The prototype consists of a single-stage full-crossbar opto-electronic switching fabric, super-packet buffers for input queuing, and a desynchronized-round-robin scheduler. The switching fabric is upgradable up to 2.56 Tb/s, and employs wavelength-division-multiplexing techniques, which dramatically reduce the total number of optical switching elements down to one-eighth the number of those used in a conventional switching fabric. The super-packet buffer assembles 16 ATM cells routed to the same output port into a single fixed-length packet. The super-packet-switching scheme drastically reduces the overhead of optical switching from 32 to 2.9%, although it tends to decrease effective throughput. The desynchronized-round-robin scheduler maintains nearly 100% effective throughput for random traffic, recursively resolving the contention of connection requests in one scheduling routine while keeping fairness in a round robin manner. The proposed Photonic Core Node can accommodate not only ATM switching but also WDM optical path grooming/multiplexing, and IP routing by using IP input buffer interfaces, because optical switches are bit-rate/format-independent.