IEICE TRANSACTIONS on Electronics
A 10-Gb/s Optical Asynchronous Packet Receiver with a Fast Bit-Synchronization Circuit
Summary :
A novel 10-Gb/s fast acquisition bit-synchronization circuit for use in a Tb/s throughput optical packet switch has been developed. The circuit is a best-sampled-data-select type based on multiple phase-clocks, and it processes the asynchronous input packets into a synchronous data stream in a serial manner, which is advantageous in terms of circuit scale and consumption power compared with the parallel processing type. The circuit was developed using Si-bipolar ultrahigh-speed gate arrays and it was used to develop a 10-Gb/s optical asynchronous packet receiver module. The core logic of this circuit module required about 100 gates, consume 6 W, and the size of the module was reduced to only 170 mm (W)
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E82-C No.8 pp.1387-1392
- Publication Date
- 1999/08/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Joint Special Issue on Recent Progress in Optoelectronics and Communications)
- Category
- Communication Networks
Authors
Keyword
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Akio TAJIMA, Hiroaki TAKAHASHI, Yoshiharu MAENO, Soichiro ARAKI, Naoya HENMI, "A 10-Gb/s Optical Asynchronous Packet Receiver with a Fast Bit-Synchronization Circuit" in IEICE TRANSACTIONS on Electronics,
vol. E82-C, no. 8, pp. 1387-1392, August 1999, doi: .
Abstract: A novel 10-Gb/s fast acquisition bit-synchronization circuit for use in a Tb/s throughput optical packet switch has been developed. The circuit is a best-sampled-data-select type based on multiple phase-clocks, and it processes the asynchronous input packets into a synchronous data stream in a serial manner, which is advantageous in terms of circuit scale and consumption power compared with the parallel processing type. The circuit was developed using Si-bipolar ultrahigh-speed gate arrays and it was used to develop a 10-Gb/s optical asynchronous packet receiver module. The core logic of this circuit module required about 100 gates, consume 6 W, and the size of the module was reduced to only 170 mm (W)
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e82-c_8_1387/_p
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@ARTICLE{e82-c_8_1387,
author={Akio TAJIMA, Hiroaki TAKAHASHI, Yoshiharu MAENO, Soichiro ARAKI, Naoya HENMI, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 10-Gb/s Optical Asynchronous Packet Receiver with a Fast Bit-Synchronization Circuit},
year={1999},
volume={E82-C},
number={8},
pages={1387-1392},
abstract={A novel 10-Gb/s fast acquisition bit-synchronization circuit for use in a Tb/s throughput optical packet switch has been developed. The circuit is a best-sampled-data-select type based on multiple phase-clocks, and it processes the asynchronous input packets into a synchronous data stream in a serial manner, which is advantageous in terms of circuit scale and consumption power compared with the parallel processing type. The circuit was developed using Si-bipolar ultrahigh-speed gate arrays and it was used to develop a 10-Gb/s optical asynchronous packet receiver module. The core logic of this circuit module required about 100 gates, consume 6 W, and the size of the module was reduced to only 170 mm (W)
keywords={},
doi={},
ISSN={},
month={August},}
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TY - JOUR
TI - A 10-Gb/s Optical Asynchronous Packet Receiver with a Fast Bit-Synchronization Circuit
T2 - IEICE TRANSACTIONS on Electronics
SP - 1387
EP - 1392
AU - Akio TAJIMA
AU - Hiroaki TAKAHASHI
AU - Yoshiharu MAENO
AU - Soichiro ARAKI
AU - Naoya HENMI
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E82-C
IS - 8
JA - IEICE TRANSACTIONS on Electronics
Y1 - August 1999
AB - A novel 10-Gb/s fast acquisition bit-synchronization circuit for use in a Tb/s throughput optical packet switch has been developed. The circuit is a best-sampled-data-select type based on multiple phase-clocks, and it processes the asynchronous input packets into a synchronous data stream in a serial manner, which is advantageous in terms of circuit scale and consumption power compared with the parallel processing type. The circuit was developed using Si-bipolar ultrahigh-speed gate arrays and it was used to develop a 10-Gb/s optical asynchronous packet receiver module. The core logic of this circuit module required about 100 gates, consume 6 W, and the size of the module was reduced to only 170 mm (W)
ER -
English
