IEICE TRANSACTIONS on Communications
Efficient Implementation of OFDM Inner Receiver on a Programmable Multi-Core Processor Platform
Summary :
This paper presents an efficient implementation of OFDM inner receiver on a programmable multi-core processor platform with CMMB as an application. The platform consists of an array of programmable SIMD processors interconnected in a 2-D mesh network, which can provide high performance and is quite suitable for wireless communication applications. Implemented on one cluster with 8 cores, the receiver includes symbol timing, carrier frequency offset and sampling frequency offset synchronization, channel estimation and equalization. Multiple optimization techniques are explored to improve system throughput such as: task-level parallelism on many cores, data-level parallelism on SIMD cores, minimization of memory access and route-length-minimization task mapping techniques. Besides, efficient memory strategy and specific instructions for complex computation increase the performance. The simulation results show that the inner receiver could achieve a throughput of up to 120 Mbps when operating at 750 MHz.
- Publication
- IEICE TRANSACTIONS on Communications Vol.E95-B No.4 pp.1241-1248
- Publication Date
- 2012/04/01
- Publicized
- Online ISSN
- 1745-1345
- DOI
- 10.1587/transcom.E95.B.1241
- Type of Manuscript
- Special Section PAPER (Special Section on Cognitive Radio and Heterogeneous Wireless Networks in Conjunction with Main Topics of CrownCom2011)
- Category
Authors
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Wenhua FAN, Chen CHEN, Yun CHEN, Zhiyi YU, Xiaoyang ZENG, "Efficient Implementation of OFDM Inner Receiver on a Programmable Multi-Core Processor Platform" in IEICE TRANSACTIONS on Communications,
vol. E95-B, no. 4, pp. 1241-1248, April 2012, doi: 10.1587/transcom.E95.B.1241.
Abstract: This paper presents an efficient implementation of OFDM inner receiver on a programmable multi-core processor platform with CMMB as an application. The platform consists of an array of programmable SIMD processors interconnected in a 2-D mesh network, which can provide high performance and is quite suitable for wireless communication applications. Implemented on one cluster with 8 cores, the receiver includes symbol timing, carrier frequency offset and sampling frequency offset synchronization, channel estimation and equalization. Multiple optimization techniques are explored to improve system throughput such as: task-level parallelism on many cores, data-level parallelism on SIMD cores, minimization of memory access and route-length-minimization task mapping techniques. Besides, efficient memory strategy and specific instructions for complex computation increase the performance. The simulation results show that the inner receiver could achieve a throughput of up to 120 Mbps when operating at 750 MHz.
URL: https://global.ieice.org/en_transactions/communications/10.1587/transcom.E95.B.1241/_p
Copy
@ARTICLE{e95-b_4_1241,
author={Wenhua FAN, Chen CHEN, Yun CHEN, Zhiyi YU, Xiaoyang ZENG, },
journal={IEICE TRANSACTIONS on Communications},
title={Efficient Implementation of OFDM Inner Receiver on a Programmable Multi-Core Processor Platform},
year={2012},
volume={E95-B},
number={4},
pages={1241-1248},
abstract={This paper presents an efficient implementation of OFDM inner receiver on a programmable multi-core processor platform with CMMB as an application. The platform consists of an array of programmable SIMD processors interconnected in a 2-D mesh network, which can provide high performance and is quite suitable for wireless communication applications. Implemented on one cluster with 8 cores, the receiver includes symbol timing, carrier frequency offset and sampling frequency offset synchronization, channel estimation and equalization. Multiple optimization techniques are explored to improve system throughput such as: task-level parallelism on many cores, data-level parallelism on SIMD cores, minimization of memory access and route-length-minimization task mapping techniques. Besides, efficient memory strategy and specific instructions for complex computation increase the performance. The simulation results show that the inner receiver could achieve a throughput of up to 120 Mbps when operating at 750 MHz.},
keywords={},
doi={10.1587/transcom.E95.B.1241},
ISSN={1745-1345},
month={April},}
Copy
TY - JOUR
TI - Efficient Implementation of OFDM Inner Receiver on a Programmable Multi-Core Processor Platform
T2 - IEICE TRANSACTIONS on Communications
SP - 1241
EP - 1248
AU - Wenhua FAN
AU - Chen CHEN
AU - Yun CHEN
AU - Zhiyi YU
AU - Xiaoyang ZENG
PY - 2012
DO - 10.1587/transcom.E95.B.1241
JO - IEICE TRANSACTIONS on Communications
SN - 1745-1345
VL - E95-B
IS - 4
JA - IEICE TRANSACTIONS on Communications
Y1 - April 2012
AB - This paper presents an efficient implementation of OFDM inner receiver on a programmable multi-core processor platform with CMMB as an application. The platform consists of an array of programmable SIMD processors interconnected in a 2-D mesh network, which can provide high performance and is quite suitable for wireless communication applications. Implemented on one cluster with 8 cores, the receiver includes symbol timing, carrier frequency offset and sampling frequency offset synchronization, channel estimation and equalization. Multiple optimization techniques are explored to improve system throughput such as: task-level parallelism on many cores, data-level parallelism on SIMD cores, minimization of memory access and route-length-minimization task mapping techniques. Besides, efficient memory strategy and specific instructions for complex computation increase the performance. The simulation results show that the inner receiver could achieve a throughput of up to 120 Mbps when operating at 750 MHz.
ER -
English
