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IEICE TRANSACTIONS on Electronics

Novel via Chain Structure for Failure Analysis at 65 nm-Node Fixing OPC Using Inner and Outer via Chain Dummy Patterns

Takashi NASUNO, Yoshihisa MATSUBARA, Hiromasa KOBAYASHI, Akiyuki MINAMI, Eiichi SODA, Hiroshi TSUDA, Koichiro TSUJITA, Wataru WAKAMIYA, Nobuyoshi KOBAYASHI

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Summary :

A novel via chain structure for failure analysis at 65 nm-node fixing OPC using inner and outer via chain dummy patterns has been proposed. The inner dummy is necessary to localize failure site in 200 nm pitch via chain using an optical beam induced resistance change method. The outer dummy protects via chain pattern from local flare and optical proximity effects. Using this test structure, we can identify the failure point in the 1.2 k and 15 k via chain fabricated by Cu/low-k single damascene process. This test structure is beneficial in the application to the 65 nm-node technologies and beyond.

Publication
IEICE TRANSACTIONS on Electronics Vol.E88-C No.5 pp.796-803
Publication Date
2005/05/01
Publicized
Online ISSN
DOI
10.1093/ietele/e88-c.5.796
Type of Manuscript
Special Section PAPER (Special Section on Microelectronic Test Structures)
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