In order to accelerate yield improvement in semiconductor manufacturing, it is important to prevent the root causes of product-specific failures, such as systematic defects and parametric defects, which are different for each product. We herein propose a method for the investigation of product-specific failures by estimating differences between the actual failing bit signatures (FBSs) and the predicted FBSs caused by random defects. In order to estimate these differences accurately, we have developed a novel algorithm by which to extract the critical area for each FBS. The total failure rate errors of FBSs are within 0.5% for embedded SRAMs. The proposed method identified the root causes of product-specific failures in 150 and 65 nm technology node products.

We have proposed and successfully demonstrated a two step method for localizing defects on an LSI chip. The first step is the same as a conventional laser-SQUID (L-SQUID) imaging where a SQUID and a laser beam are fixed during LSI chip scanning. The second step is a new L-SQUID imaging where a laser beam is stayed at the point, located in the first step results, during SQUID scanning. In the second step, a SQUID size (Aeff) and the distance between the SQUID and the LSI chip (ΔZ) are key factors limiting spatial resolution. In order to improve the spatial resolution, we have developed a micro-SQUID and the vacuum chamber housing both the micro-SQUID and the LSI chip. The Aeff of the micro-SQUID is a thousand of that of a conventional SQUID. The minimum value of ΔZ was successfully reduced to 25 µm by setting both the micro-SQUID and an LSI chip in the same vacuum chamber. The spatial resolution in the second step was shown to be 53 µm. Demonstration of actual complicated defects localization was succeeded, and this result suggests that the two step localization method is useful for LSI failure analysis.

To improve product yield in high-product-mix semiconductor manufacturing, it is important to estimate the systematic yield inherent to each product and to extract problematic products that have low systematic yields. We propose a simplified and available yield model using a critical area analysis. This model enables the extraction of problematic products by the relationship between actual yields and the short sensitivities of the products. Furthermore, we present an enterprise-wide yield management system using this model and some useful applications. As a result, the system increases the efficiency of the yield management and enhancement dramatically.

The fast handover protocol adopted in a IPv6 hierarchical structure provides a seamless handover in wireless IP networks by minimizing the handover latency. To reduce the handover latency, the fast handover uses anticipation based on layer 2 trigger. Nonetheless, a mobile node can still lose its connection with the old link during the fast handover procedures. Accordingly, this paper analyzes the handover latency and packet delivery costs associated with fast handover failure cases based on a timing diagram.

This work proposes a technique to automatically obtain timing constraints for a given timed circuit to operate correctly. A designated set of delay parameters of a circuit are first set to sufficiently large bounds, and verification runs followed by failure analysis are repeated. Each verification run performs timed state space enumeration under the given delay bounds, and produces a failure trace if it exists. The failure trace is analyzed, and sufficient timing constraints to prevent the failure are obtained. Then, the delay bounds are tightened according to the timing constraints by using an ILP (Integer Linear Programming) solver. This process terminates when either some delay bounds under which no failure is detected are found or no new delay bounds to prevent the failures can be obtained. The experimental results using a naive implementation show that the proposed method can efficiently handle asynchronous benchmark circuits and nontrivial GasP circuits.

A novel via chain structure for failure analysis at 65 nm-node fixing OPC using inner and outer via chain dummy patterns has been proposed. The inner dummy is necessary to localize failure site in 200 nm pitch via chain using an optical beam induced resistance change method. The outer dummy protects via chain pattern from local flare and optical proximity effects. Using this test structure, we can identify the failure point in the 1.2 k and 15 k via chain fabricated by Cu/low-k single damascene process. This test structure is beneficial in the application to the 65 nm-node technologies and beyond.

We have developed and demonstrated a novel technique for electrical inspection and electrical failure analysis, which can detect open, high-resistance, and short circuits without the need for electrical contact with the outside of the LSI chip or the board on which the LSI chip is mounted. The basic idea of the technique is the detection of the magnetic field produced by OBIC (optical beam induced current) or photo current. A DC-SQUID (superconducting quantum interference device) magnetometer is used to detect the magnetic field. This scanning laser-SQUID microscopy ("laser-SQUID" for short) has a spatial resolution of about 1.3 µm. It can be used to distinguish defective chips before bonding pad patterning or after bonding without pin-selection. It can localize any defective site in the chip to within a few square microns.

We have improved the optical beam induced resistance change (OBIRCH) system so as to detect (1) a current path as small as 10-50 µA from the rear side of a chip, (2) current paths in silicide lines as narrow as 0. 2 µm, (3) high-resistance Ti-depleted polysilicon regions in 0. 2 µm wide silicide lines, and (4) high-resistance amorphous thin layers as thin as a few nanometers at the bottoms of vias. All detections were possible even in observation areas as wide as 5 mm 5 mm. The physical causes of these detections were characterized by focused ion beam and transmission electron microscopy.

A new observation technique for process-induced micro-defects in ULSI using a combination of anodic oxidation and chemical removal of the oxide has been developed. Enhanced oxidation has occurred at the defect region due to the stress field and then craterlike delineation has been formed after oxide removal. AFM and SEM observation of the micro-defects induced by ion implantation and applications using this tech-nique to the failure analysis of MOS device fabrication are presented.

A detabase system that provides step-by-step guidance for LSI failure analysts has been developed. This system has three main functions: database, navigator, and chip tracking. The datebase stores failure analysis information such as analysis method and failure mechanisms including image data. It also stores conditions and results of each analysis step and decisions to proceeds to the next analysis step. With 2000 failure analysis cases, data retrieval takes 6.6 seconds, a table containing 20 photos is presented in 6.5 seconds, and a different set of data can be displayed in 0.6 seconds. The navigator displays a standard analysis procedure illustrated in flow charts.The chip tracking shows where the particular chip is and what analysis it is undergoing, which is useful for the situation where many chips are simultaneously analyzed. Thus, this system has good enough functions of analysis procedure management and performance of quick data access to make failure analysis easier and more successful.

The mechanism for data retention failure of EPROM has been investigated by the Optical Beam Induced Current(OBIC) technique. It was found that the data of failure cells were changed from '1' to '0' during read-mode by laser irradiation by OBIC. The data in good cells was not changed. This result suggests the effective barrier height between Si and SiO2 is being lowered. In addition, the cross section technique revealed that gate electrode and gate oxide were exposed due to lack of dielectric layers. This defect seemed to be the cause of the barrier height lowering. The OBIC technique not only gives the failure location but a detailed information of the failure mechanism. We found that OBIC technique is a very powerful tool for the analysis of EPROM failure mechanisms. The usefulness of the Emission Micro Scope (EMS) technique is also discussed.

The origin of and a method of enhancing the Optical Beam Induced Resistance Change (OBIRCH) signal for defect observation in VLSI metal interconnections is discussed based on a numerical analysis of three-dimensional thermal conduction and experimental results. The numerical analysis shows that the OBIRCH signal originates from a slight increase in the resistance of the metal line caused by laser beam heating and that its effect is influenced by the temperature of the metal layer. Both simulations and experimental results suggest that cooling the sample is preferable to detect the OBIRCH signal. The decrease in the total resistance of the metal line without any change in the amount of the resistance increase under laser illumination is found to be the main cause of the OBIRCH signal enhancement under low temperature measurement.

Following a discussion of various testing methods used in the electron beam (EB) test system, new waveform-based and image-based approaches in the CAD-linked electron beam (EB) test system are proposed. A waveform-based automatic tracing algorithm of the transistor-level performance faults is first discussed. Then, the method to improve the efficiency of an image-based method called dynamic fault imaging (DFI) by fully utilizing the CAD data is described. Third, the VLSI development cost is analyzed by using the fault models that make possible to take into consideration the effect of new testing technologies such as EB testing and focused ion beam (FIB) microfabrication. Finally, the future prospects are discussed.