IEICE TRANSACTIONS on Electronics
A New Inductance Extraction Technique of On-Wafer Spiral Inductor Based on Analytical Interconnect Formula
Summary :
A new inductance extraction technique of spiral inductor from measurement fixture is presented. We propose a scalable expression of parasitic inductance for interconnects, and design consideration of test structure accommodating spiral inductor. The simple expression includes mutual inductance between the interconnects with high accuracy. The formula matches a commercial field solver inductance values within 1.4%. The layout of the test structure to reduce magnetic coupling between the spiral and the interconnects allows us to extract the intrinsic inductance of spiral more accurately. The proposed technique requires neither special fixture used for measurement-based method nor skilled worker for precise extraction with the analytical technique used.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E88-C No.5 pp.824-828
- Publication Date
- 2005/05/01
- Publicized
- Online ISSN
- DOI
- 10.1093/ietele/e88-c.5.824
- Type of Manuscript
- Special Section PAPER (Special Section on Microelectronic Test Structures)
- Category
Authors
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Hideki SHIMA, Toshimasa MATSUOKA, Kenji TANIGUCHI, "A New Inductance Extraction Technique of On-Wafer Spiral Inductor Based on Analytical Interconnect Formula" in IEICE TRANSACTIONS on Electronics,
vol. E88-C, no. 5, pp. 824-828, May 2005, doi: 10.1093/ietele/e88-c.5.824.
Abstract: A new inductance extraction technique of spiral inductor from measurement fixture is presented. We propose a scalable expression of parasitic inductance for interconnects, and design consideration of test structure accommodating spiral inductor. The simple expression includes mutual inductance between the interconnects with high accuracy. The formula matches a commercial field solver inductance values within 1.4%. The layout of the test structure to reduce magnetic coupling between the spiral and the interconnects allows us to extract the intrinsic inductance of spiral more accurately. The proposed technique requires neither special fixture used for measurement-based method nor skilled worker for precise extraction with the analytical technique used.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e88-c.5.824/_p
Copy
@ARTICLE{e88-c_5_824,
author={Hideki SHIMA, Toshimasa MATSUOKA, Kenji TANIGUCHI, },
journal={IEICE TRANSACTIONS on Electronics},
title={A New Inductance Extraction Technique of On-Wafer Spiral Inductor Based on Analytical Interconnect Formula},
year={2005},
volume={E88-C},
number={5},
pages={824-828},
abstract={A new inductance extraction technique of spiral inductor from measurement fixture is presented. We propose a scalable expression of parasitic inductance for interconnects, and design consideration of test structure accommodating spiral inductor. The simple expression includes mutual inductance between the interconnects with high accuracy. The formula matches a commercial field solver inductance values within 1.4%. The layout of the test structure to reduce magnetic coupling between the spiral and the interconnects allows us to extract the intrinsic inductance of spiral more accurately. The proposed technique requires neither special fixture used for measurement-based method nor skilled worker for precise extraction with the analytical technique used.},
keywords={},
doi={10.1093/ietele/e88-c.5.824},
ISSN={},
month={May},}
Copy
TY - JOUR
TI - A New Inductance Extraction Technique of On-Wafer Spiral Inductor Based on Analytical Interconnect Formula
T2 - IEICE TRANSACTIONS on Electronics
SP - 824
EP - 828
AU - Hideki SHIMA
AU - Toshimasa MATSUOKA
AU - Kenji TANIGUCHI
PY - 2005
DO - 10.1093/ietele/e88-c.5.824
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E88-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 2005
AB - A new inductance extraction technique of spiral inductor from measurement fixture is presented. We propose a scalable expression of parasitic inductance for interconnects, and design consideration of test structure accommodating spiral inductor. The simple expression includes mutual inductance between the interconnects with high accuracy. The formula matches a commercial field solver inductance values within 1.4%. The layout of the test structure to reduce magnetic coupling between the spiral and the interconnects allows us to extract the intrinsic inductance of spiral more accurately. The proposed technique requires neither special fixture used for measurement-based method nor skilled worker for precise extraction with the analytical technique used.
ER -
English
