A Fully Integrated 1.7-3.125 Gbps Clock and Data Recovery Circuit Using a Gated Frequency Detector
Summary :
A fully integrated clock and data recovery circuit with the proposed gated frequency detector (GFD) is presented. It has been realized in a standard 0.25-µm CMOS technology. The proposed voltage-controlled oscillator (VCO) can achieve wide operation range and reasonable conversion gain by employing the analog/digital dual loop architecture. The characteristics of small VCO gain can help to reduce loop bandwidth without enlarge the capacitors and relax the constraint on choosing the loop parameter to reduce the size of the on-chip capacitor. The proposed GFD will make the frequency lock time fixed and can avoid the harmonic locking problem in digital domain for wide data rate operations. All measured BERs are less than 10-12 with the data rate from 1.7 Gbps to 3.125 Gbps.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E88-C No.8 pp.1726-1730
- Publication Date
- 2005/08/01
- Publicized
- Online ISSN
- DOI
- 10.1093/ietele/e88-c.8.1726
- Type of Manuscript
- Special Section PAPER (Special Section on Papers Selected from AP-ASIC 2004)
- Category
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Rong-Jyi YANG, Shen-Iuan LIU, "A Fully Integrated 1.7-3.125 Gbps Clock and Data Recovery Circuit Using a Gated Frequency Detector" in IEICE TRANSACTIONS on Electronics,
vol. E88-C, no. 8, pp. 1726-1730, August 2005, doi: 10.1093/ietele/e88-c.8.1726.
Abstract: A fully integrated clock and data recovery circuit with the proposed gated frequency detector (GFD) is presented. It has been realized in a standard 0.25-µm CMOS technology. The proposed voltage-controlled oscillator (VCO) can achieve wide operation range and reasonable conversion gain by employing the analog/digital dual loop architecture. The characteristics of small VCO gain can help to reduce loop bandwidth without enlarge the capacitors and relax the constraint on choosing the loop parameter to reduce the size of the on-chip capacitor. The proposed GFD will make the frequency lock time fixed and can avoid the harmonic locking problem in digital domain for wide data rate operations. All measured BERs are less than 10-12 with the data rate from 1.7 Gbps to 3.125 Gbps.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e88-c.8.1726/_p
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@ARTICLE{e88-c_8_1726,
author={Rong-Jyi YANG, Shen-Iuan LIU, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Fully Integrated 1.7-3.125 Gbps Clock and Data Recovery Circuit Using a Gated Frequency Detector},
year={2005},
volume={E88-C},
number={8},
pages={1726-1730},
abstract={A fully integrated clock and data recovery circuit with the proposed gated frequency detector (GFD) is presented. It has been realized in a standard 0.25-µm CMOS technology. The proposed voltage-controlled oscillator (VCO) can achieve wide operation range and reasonable conversion gain by employing the analog/digital dual loop architecture. The characteristics of small VCO gain can help to reduce loop bandwidth without enlarge the capacitors and relax the constraint on choosing the loop parameter to reduce the size of the on-chip capacitor. The proposed GFD will make the frequency lock time fixed and can avoid the harmonic locking problem in digital domain for wide data rate operations. All measured BERs are less than 10-12 with the data rate from 1.7 Gbps to 3.125 Gbps.},
keywords={},
doi={10.1093/ietele/e88-c.8.1726},
ISSN={},
month={August},}
Copy
TY - JOUR
TI - A Fully Integrated 1.7-3.125 Gbps Clock and Data Recovery Circuit Using a Gated Frequency Detector
T2 - IEICE TRANSACTIONS on Electronics
SP - 1726
EP - 1730
AU - Rong-Jyi YANG
AU - Shen-Iuan LIU
PY - 2005
DO - 10.1093/ietele/e88-c.8.1726
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E88-C
IS - 8
JA - IEICE TRANSACTIONS on Electronics
Y1 - August 2005
AB - A fully integrated clock and data recovery circuit with the proposed gated frequency detector (GFD) is presented. It has been realized in a standard 0.25-µm CMOS technology. The proposed voltage-controlled oscillator (VCO) can achieve wide operation range and reasonable conversion gain by employing the analog/digital dual loop architecture. The characteristics of small VCO gain can help to reduce loop bandwidth without enlarge the capacitors and relax the constraint on choosing the loop parameter to reduce the size of the on-chip capacitor. The proposed GFD will make the frequency lock time fixed and can avoid the harmonic locking problem in digital domain for wide data rate operations. All measured BERs are less than 10-12 with the data rate from 1.7 Gbps to 3.125 Gbps.
ER -
English
