A fully integrated clock and data recovery circuit with the proposed gated frequency detector (GFD) is presented. It has been realized in a standard 0.25-µm CMOS technology. The proposed voltage-controlled oscillator (VCO) can achieve wide operation range and reasonable conversion gain by employing the analog/digital dual loop architecture. The characteristics of small VCO gain can help to reduce loop bandwidth without enlarge the capacitors and relax the constraint on choosing the loop parameter to reduce the size of the on-chip capacitor. The proposed GFD will make the frequency lock time fixed and can avoid the harmonic locking problem in digital domain for wide data rate operations. All measured BERs are less than 10-12 with the data rate from 1.7 Gbps to 3.125 Gbps.

This paper describes the design of a programmable QAM transceiver for VDSL applications. A 12-b DAC with 64-dB spurious-free dynamic range (SFDR) at 75-MS/s and an 11-b ADC with 72.3-dB SFDR at 70-MS/s are integrated in this complete physical layer IC. A digital IIR notch filter is included in order to not interrupt existing amateur radio bands. The proposed dual loop AGC adjusts the gain of a variable gain amplifier (VGA) to obtain maximum SNR while avoiding saturation. Using several low power techniques, the total power consumption is reduced to 300-mW at 1.8-V core and 3.3-V I/O supplies. The transceiver is fabricated in a 0.18-µm CMOS process and the chip size is 5-mm 5-mm. This VDSL transceiver supports 13-Mbps data rate over a 9000-ft channel with a BER < 10-7.