IEICE TRANSACTIONS on Electronics
Design of Low-Noise, Low-Power 10-GHz VCO Using 0.18-µm CMOS Technology
Summary :
A low-noise, low-power 10-GHz CMOS VCO was developed using cost-effective 0.18-µm CMOS technology. A complementary cross-coupled topology was employed to decrease the power dissipation and phase noise. The fabricated VCO demonstrates a low phase noise of -106 dBc/Hz at an offset frequency of 1 MHz and a low power dissipation of 4.4 mW.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E89-C No.2 pp.203-205
- Publication Date
- 2006/02/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1093/ietele/e89-c.2.203
- Type of Manuscript
- LETTER
- Category
- Microwaves, Millimeter-Waves
Authors
Keyword
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Kenichi OHHATA, Katsuyoshi HARASAWA, Makoto HONDA, Kiichi YAMASHITA, "Design of Low-Noise, Low-Power 10-GHz VCO Using 0.18-µm CMOS Technology" in IEICE TRANSACTIONS on Electronics,
vol. E89-C, no. 2, pp. 203-205, February 2006, doi: 10.1093/ietele/e89-c.2.203.
Abstract: A low-noise, low-power 10-GHz CMOS VCO was developed using cost-effective 0.18-µm CMOS technology. A complementary cross-coupled topology was employed to decrease the power dissipation and phase noise. The fabricated VCO demonstrates a low phase noise of -106 dBc/Hz at an offset frequency of 1 MHz and a low power dissipation of 4.4 mW.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e89-c.2.203/_p
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@ARTICLE{e89-c_2_203,
author={Kenichi OHHATA, Katsuyoshi HARASAWA, Makoto HONDA, Kiichi YAMASHITA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Design of Low-Noise, Low-Power 10-GHz VCO Using 0.18-µm CMOS Technology},
year={2006},
volume={E89-C},
number={2},
pages={203-205},
abstract={A low-noise, low-power 10-GHz CMOS VCO was developed using cost-effective 0.18-µm CMOS technology. A complementary cross-coupled topology was employed to decrease the power dissipation and phase noise. The fabricated VCO demonstrates a low phase noise of -106 dBc/Hz at an offset frequency of 1 MHz and a low power dissipation of 4.4 mW.},
keywords={},
doi={10.1093/ietele/e89-c.2.203},
ISSN={1745-1353},
month={February},}
Copy
TY - JOUR
TI - Design of Low-Noise, Low-Power 10-GHz VCO Using 0.18-µm CMOS Technology
T2 - IEICE TRANSACTIONS on Electronics
SP - 203
EP - 205
AU - Kenichi OHHATA
AU - Katsuyoshi HARASAWA
AU - Makoto HONDA
AU - Kiichi YAMASHITA
PY - 2006
DO - 10.1093/ietele/e89-c.2.203
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E89-C
IS - 2
JA - IEICE TRANSACTIONS on Electronics
Y1 - February 2006
AB - A low-noise, low-power 10-GHz CMOS VCO was developed using cost-effective 0.18-µm CMOS technology. A complementary cross-coupled topology was employed to decrease the power dissipation and phase noise. The fabricated VCO demonstrates a low phase noise of -106 dBc/Hz at an offset frequency of 1 MHz and a low power dissipation of 4.4 mW.
ER -
English
