A Low-Power Instruction Issue Queue for Microprocessors

Shingo WATANABE; Akihiro CHIYONOBU; Toshinori SATO

doi:10.1093/ietele/e91-c.4.400

A Low-Power Instruction Issue Queue for Microprocessors

Shingo WATANABE, Akihiro CHIYONOBU, Toshinori SATO

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Instruction issue queue is a key component which extracts instruction level parallelism (ILP) in modern out-of-order microprocessors. In order to exploit ILP for improving processor performance, instruction queue size should be increased. However, it is difficult to increase the size, since instruction queue is implemented by a content addressable memory (CAM) whose power and delay are much large. This paper introduces a low power and scalable instruction queue that replaces the CAM with a RAM. In this queue, instructions are explicitly woken up. Evaluation results show that the proposed instruction queue decreases processor performance by only 1.9% on average. Furthermore, the total energy consumption is reduced by 54% on average.

Publication: IEICE TRANSACTIONS on Electronics Vol.E91-C No.4 pp.400-409

Publication Date: 2008/04/01

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Online ISSN: 1745-1353

DOI: 10.1093/ietele/e91-c.4.400

Type of Manuscript: Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories)

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Shingo WATANABE, Akihiro CHIYONOBU, Toshinori SATO, "A Low-Power Instruction Issue Queue for Microprocessors" in IEICE TRANSACTIONS on Electronics, vol. E91-C, no. 4, pp. 400-409, April 2008, doi: 10.1093/ietele/e91-c.4.400.
Abstract: Instruction issue queue is a key component which extracts instruction level parallelism (ILP) in modern out-of-order microprocessors. In order to exploit ILP for improving processor performance, instruction queue size should be increased. However, it is difficult to increase the size, since instruction queue is implemented by a content addressable memory (CAM) whose power and delay are much large. This paper introduces a low power and scalable instruction queue that replaces the CAM with a RAM. In this queue, instructions are explicitly woken up. Evaluation results show that the proposed instruction queue decreases processor performance by only 1.9% on average. Furthermore, the total energy consumption is reduced by 54% on average.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e91-c.4.400/_p

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@ARTICLE{e91-c_4_400,
author={Shingo WATANABE, Akihiro CHIYONOBU, Toshinori SATO, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Low-Power Instruction Issue Queue for Microprocessors},
year={2008},
volume={E91-C},
number={4},
pages={400-409},
abstract={Instruction issue queue is a key component which extracts instruction level parallelism (ILP) in modern out-of-order microprocessors. In order to exploit ILP for improving processor performance, instruction queue size should be increased. However, it is difficult to increase the size, since instruction queue is implemented by a content addressable memory (CAM) whose power and delay are much large. This paper introduces a low power and scalable instruction queue that replaces the CAM with a RAM. In this queue, instructions are explicitly woken up. Evaluation results show that the proposed instruction queue decreases processor performance by only 1.9% on average. Furthermore, the total energy consumption is reduced by 54% on average.},
keywords={},
doi={10.1093/ietele/e91-c.4.400},
ISSN={1745-1353},
month={April},}

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TY - JOUR
TI - A Low-Power Instruction Issue Queue for Microprocessors
T2 - IEICE TRANSACTIONS on Electronics
SP - 400
EP - 409
AU - Shingo WATANABE
AU - Akihiro CHIYONOBU
AU - Toshinori SATO
PY - 2008
DO - 10.1093/ietele/e91-c.4.400
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E91-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2008
AB - Instruction issue queue is a key component which extracts instruction level parallelism (ILP) in modern out-of-order microprocessors. In order to exploit ILP for improving processor performance, instruction queue size should be increased. However, it is difficult to increase the size, since instruction queue is implemented by a content addressable memory (CAM) whose power and delay are much large. This paper introduces a low power and scalable instruction queue that replaces the CAM with a RAM. In this queue, instructions are explicitly woken up. Evaluation results show that the proposed instruction queue decreases processor performance by only 1.9% on average. Furthermore, the total energy consumption is reduced by 54% on average.
ER -