IEICE TRANSACTIONS on Electronics
LSI Implementation and Safety Verification of Window Comparator Used in Fail-Safe Multiple-Valued Logic Operations
Summary :
A fail-safe logic operation refers to such a processing operation that the output assumes the logical value zero when the operation circuit fails. The fail-safe multiple-valued logic operation is proposed as one method of logic operation. Section 2 defines the fail-asfe multiple-valued logic operation and presents an example of method for accomplishing the fail-safe multiple-valued logic operation. Section 3 describes the method of designing a fail-safe threshold operation device (window comparator) as basic device in the fail-safe multiple-valued logic operation in consideration of LSI implementation and shows an example of prototype fail-safe window comparator. This operation device has higher and lower thresholds. It oscillates and produces an operational output signal only when the input signal level falls between the higher and lower thresholds. Unless the fail-safe window comparator is supplied with input signals of higher voltage than the power supply voltage, it dose not form a feedbadk loop as required for it to oscillate. This characteristic prevents the device from erroneously producing an output signal when any failure occurs in the amplifiers comprising the oscillation circuit. The window comparator can be built as a fail-safe threshold operation device. The fail-safe characteristic is utilized in its LSI implementation. Section 4 verifies the fail-safe property of the prortotype fail-safe window comparator. It is shown that even when the LSI develops failures not evident from outsid (latent failures), it does not lose the operational function and maintains the fail-safe characteristic.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E76-C No.3 pp.419-427
- Publication Date
- 1993/03/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on Multiple-Valued Integrated Circuits)
- Category
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Masakazu KATO, Masayoshi SAKAI, Koji JINKAWA, Koichi FUTSUHARA, Masao MUKAIDONO, "LSI Implementation and Safety Verification of Window Comparator Used in Fail-Safe Multiple-Valued Logic Operations" in IEICE TRANSACTIONS on Electronics,
vol. E76-C, no. 3, pp. 419-427, March 1993, doi: .
Abstract: A fail-safe logic operation refers to such a processing operation that the output assumes the logical value zero when the operation circuit fails. The fail-safe multiple-valued logic operation is proposed as one method of logic operation. Section 2 defines the fail-asfe multiple-valued logic operation and presents an example of method for accomplishing the fail-safe multiple-valued logic operation. Section 3 describes the method of designing a fail-safe threshold operation device (window comparator) as basic device in the fail-safe multiple-valued logic operation in consideration of LSI implementation and shows an example of prototype fail-safe window comparator. This operation device has higher and lower thresholds. It oscillates and produces an operational output signal only when the input signal level falls between the higher and lower thresholds. Unless the fail-safe window comparator is supplied with input signals of higher voltage than the power supply voltage, it dose not form a feedbadk loop as required for it to oscillate. This characteristic prevents the device from erroneously producing an output signal when any failure occurs in the amplifiers comprising the oscillation circuit. The window comparator can be built as a fail-safe threshold operation device. The fail-safe characteristic is utilized in its LSI implementation. Section 4 verifies the fail-safe property of the prortotype fail-safe window comparator. It is shown that even when the LSI develops failures not evident from outsid (latent failures), it does not lose the operational function and maintains the fail-safe characteristic.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e76-c_3_419/_p
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@ARTICLE{e76-c_3_419,
author={Masakazu KATO, Masayoshi SAKAI, Koji JINKAWA, Koichi FUTSUHARA, Masao MUKAIDONO, },
journal={IEICE TRANSACTIONS on Electronics},
title={LSI Implementation and Safety Verification of Window Comparator Used in Fail-Safe Multiple-Valued Logic Operations},
year={1993},
volume={E76-C},
number={3},
pages={419-427},
abstract={A fail-safe logic operation refers to such a processing operation that the output assumes the logical value zero when the operation circuit fails. The fail-safe multiple-valued logic operation is proposed as one method of logic operation. Section 2 defines the fail-asfe multiple-valued logic operation and presents an example of method for accomplishing the fail-safe multiple-valued logic operation. Section 3 describes the method of designing a fail-safe threshold operation device (window comparator) as basic device in the fail-safe multiple-valued logic operation in consideration of LSI implementation and shows an example of prototype fail-safe window comparator. This operation device has higher and lower thresholds. It oscillates and produces an operational output signal only when the input signal level falls between the higher and lower thresholds. Unless the fail-safe window comparator is supplied with input signals of higher voltage than the power supply voltage, it dose not form a feedbadk loop as required for it to oscillate. This characteristic prevents the device from erroneously producing an output signal when any failure occurs in the amplifiers comprising the oscillation circuit. The window comparator can be built as a fail-safe threshold operation device. The fail-safe characteristic is utilized in its LSI implementation. Section 4 verifies the fail-safe property of the prortotype fail-safe window comparator. It is shown that even when the LSI develops failures not evident from outsid (latent failures), it does not lose the operational function and maintains the fail-safe characteristic.},
keywords={},
doi={},
ISSN={},
month={March},}
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TY - JOUR
TI - LSI Implementation and Safety Verification of Window Comparator Used in Fail-Safe Multiple-Valued Logic Operations
T2 - IEICE TRANSACTIONS on Electronics
SP - 419
EP - 427
AU - Masakazu KATO
AU - Masayoshi SAKAI
AU - Koji JINKAWA
AU - Koichi FUTSUHARA
AU - Masao MUKAIDONO
PY - 1993
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E76-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 1993
AB - A fail-safe logic operation refers to such a processing operation that the output assumes the logical value zero when the operation circuit fails. The fail-safe multiple-valued logic operation is proposed as one method of logic operation. Section 2 defines the fail-asfe multiple-valued logic operation and presents an example of method for accomplishing the fail-safe multiple-valued logic operation. Section 3 describes the method of designing a fail-safe threshold operation device (window comparator) as basic device in the fail-safe multiple-valued logic operation in consideration of LSI implementation and shows an example of prototype fail-safe window comparator. This operation device has higher and lower thresholds. It oscillates and produces an operational output signal only when the input signal level falls between the higher and lower thresholds. Unless the fail-safe window comparator is supplied with input signals of higher voltage than the power supply voltage, it dose not form a feedbadk loop as required for it to oscillate. This characteristic prevents the device from erroneously producing an output signal when any failure occurs in the amplifiers comprising the oscillation circuit. The window comparator can be built as a fail-safe threshold operation device. The fail-safe characteristic is utilized in its LSI implementation. Section 4 verifies the fail-safe property of the prortotype fail-safe window comparator. It is shown that even when the LSI develops failures not evident from outsid (latent failures), it does not lose the operational function and maintains the fail-safe characteristic.
ER -
English
