Hardware Architecture for Kohonen Network

Hidetoshi ONODERA; Kiyoshi TAKESHITA; Keikichi TAMARU

Hardware Architecture for Kohonen Network

Hidetoshi ONODERA, Kiyoshi TAKESHITA, Keikichi TAMARU

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We propose a fully digital architecture for Kohonen network suitable for VLSI implementation. The proposed architecture adopts a functional memory type parallel processor (FMPP) architecture which has a structure similar to a content addressable memory (CAM). One word of CAM is regarded as a processing element and a group of elements forms a neuron. All processing elements execute the same operation in bit-serial but in processor-parallel. Thus the number of instructions for realizing the network algorithm is independent of the number of neurons in the network. With reference to a previously reported CAM, we estimate a network with 96 neurons for speech recognition could be integrated on three chips using a 1.2 µm process, and it operates 50 times faster than a sequential hardware. Owing to its highly regular structure of memories, the proposed hardware architecture is well compatible with current VLSI technology.

Publication: IEICE TRANSACTIONS on Electronics Vol.E76-C No.7 pp.1159-1166

Publication Date: 1993/07/25

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Type of Manuscript: Special Section PAPER (Special Issue on New Architecture LSIs)

Category: Neural Networks and Chips

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Hidetoshi ONODERA, Kiyoshi TAKESHITA, Keikichi TAMARU, "Hardware Architecture for Kohonen Network" in IEICE TRANSACTIONS on Electronics, vol. E76-C, no. 7, pp. 1159-1166, July 1993, doi: .
Abstract: We propose a fully digital architecture for Kohonen network suitable for VLSI implementation. The proposed architecture adopts a functional memory type parallel processor (FMPP) architecture which has a structure similar to a content addressable memory (CAM). One word of CAM is regarded as a processing element and a group of elements forms a neuron. All processing elements execute the same operation in bit-serial but in processor-parallel. Thus the number of instructions for realizing the network algorithm is independent of the number of neurons in the network. With reference to a previously reported CAM, we estimate a network with 96 neurons for speech recognition could be integrated on three chips using a 1.2 µm process, and it operates 50 times faster than a sequential hardware. Owing to its highly regular structure of memories, the proposed hardware architecture is well compatible with current VLSI technology.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e76-c_7_1159/_p

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@ARTICLE{e76-c_7_1159,
author={Hidetoshi ONODERA, Kiyoshi TAKESHITA, Keikichi TAMARU, },
journal={IEICE TRANSACTIONS on Electronics},
title={Hardware Architecture for Kohonen Network},
year={1993},
volume={E76-C},
number={7},
pages={1159-1166},
abstract={We propose a fully digital architecture for Kohonen network suitable for VLSI implementation. The proposed architecture adopts a functional memory type parallel processor (FMPP) architecture which has a structure similar to a content addressable memory (CAM). One word of CAM is regarded as a processing element and a group of elements forms a neuron. All processing elements execute the same operation in bit-serial but in processor-parallel. Thus the number of instructions for realizing the network algorithm is independent of the number of neurons in the network. With reference to a previously reported CAM, we estimate a network with 96 neurons for speech recognition could be integrated on three chips using a 1.2 µm process, and it operates 50 times faster than a sequential hardware. Owing to its highly regular structure of memories, the proposed hardware architecture is well compatible with current VLSI technology.},
keywords={},
doi={},
ISSN={},
month={July},}

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TY - JOUR
TI - Hardware Architecture for Kohonen Network
T2 - IEICE TRANSACTIONS on Electronics
SP - 1159
EP - 1166
AU - Hidetoshi ONODERA
AU - Kiyoshi TAKESHITA
AU - Keikichi TAMARU
PY - 1993
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E76-C
IS - 7
JA - IEICE TRANSACTIONS on Electronics
Y1 - July 1993
AB - We propose a fully digital architecture for Kohonen network suitable for VLSI implementation. The proposed architecture adopts a functional memory type parallel processor (FMPP) architecture which has a structure similar to a content addressable memory (CAM). One word of CAM is regarded as a processing element and a group of elements forms a neuron. All processing elements execute the same operation in bit-serial but in processor-parallel. Thus the number of instructions for realizing the network algorithm is independent of the number of neurons in the network. With reference to a previously reported CAM, we estimate a network with 96 neurons for speech recognition could be integrated on three chips using a 1.2 µm process, and it operates 50 times faster than a sequential hardware. Owing to its highly regular structure of memories, the proposed hardware architecture is well compatible with current VLSI technology.
ER -