Development and Fabrication of Digital Neural Network WSIs

Minoru FUJITA; Yasushi KOBAYASHI; Kenji SHIOZAWA; Takahiko TAKAHASHI; Fumio MIZUNO; Hajime HAYAKAWA; Makoto KATO; Shigeki MORI; Tetsuro KASE; Minoru YAMADA

Development and Fabrication of Digital Neural Network WSIs

Minoru FUJITA, Yasushi KOBAYASHI, Kenji SHIOZAWA, Takahiko TAKAHASHI, Fumio MIZUNO, Hajime HAYAKAWA, Makoto KATO, Shigeki MORI, Tetsuro KASE, Minoru YAMADA

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Digital neural networks are suitable for WSI implementation because their noise immunity is high, they have a fault tolerant structure, and the use of bus architecture can reduce the number of interconnections between neurons. To investigate the feasibility of WSIs, we integrated either 576 conventional neurons or 288 self-learning neurons on a 5-inch wafer, by using 0.8-µm CMOS technology and three metal layers. We also developed a new electron-beam direct-writing technology which enables easier fabrication of VLSI chips and wafer-level interconnections. We fabricated 288 self-learning neuron WSIs having as many as 230 good neurons.

Publication: IEICE TRANSACTIONS on Electronics Vol.E76-C No.7 pp.1182-1190

Publication Date: 1993/07/25

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Type of Manuscript: Special Section PAPER (Special Issue on New Architecture LSIs)

Category: Neural Networks and Chips

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Minoru FUJITA, Yasushi KOBAYASHI, Kenji SHIOZAWA, Takahiko TAKAHASHI, Fumio MIZUNO, Hajime HAYAKAWA, Makoto KATO, Shigeki MORI, Tetsuro KASE, Minoru YAMADA, "Development and Fabrication of Digital Neural Network WSIs" in IEICE TRANSACTIONS on Electronics, vol. E76-C, no. 7, pp. 1182-1190, July 1993, doi: .
Abstract: Digital neural networks are suitable for WSI implementation because their noise immunity is high, they have a fault tolerant structure, and the use of bus architecture can reduce the number of interconnections between neurons. To investigate the feasibility of WSIs, we integrated either 576 conventional neurons or 288 self-learning neurons on a 5-inch wafer, by using 0.8-µm CMOS technology and three metal layers. We also developed a new electron-beam direct-writing technology which enables easier fabrication of VLSI chips and wafer-level interconnections. We fabricated 288 self-learning neuron WSIs having as many as 230 good neurons.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e76-c_7_1182/_p

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@ARTICLE{e76-c_7_1182,
author={Minoru FUJITA, Yasushi KOBAYASHI, Kenji SHIOZAWA, Takahiko TAKAHASHI, Fumio MIZUNO, Hajime HAYAKAWA, Makoto KATO, Shigeki MORI, Tetsuro KASE, Minoru YAMADA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Development and Fabrication of Digital Neural Network WSIs},
year={1993},
volume={E76-C},
number={7},
pages={1182-1190},
abstract={Digital neural networks are suitable for WSI implementation because their noise immunity is high, they have a fault tolerant structure, and the use of bus architecture can reduce the number of interconnections between neurons. To investigate the feasibility of WSIs, we integrated either 576 conventional neurons or 288 self-learning neurons on a 5-inch wafer, by using 0.8-µm CMOS technology and three metal layers. We also developed a new electron-beam direct-writing technology which enables easier fabrication of VLSI chips and wafer-level interconnections. We fabricated 288 self-learning neuron WSIs having as many as 230 good neurons.},
keywords={},
doi={},
ISSN={},
month={July},}

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TY - JOUR
TI - Development and Fabrication of Digital Neural Network WSIs
T2 - IEICE TRANSACTIONS on Electronics
SP - 1182
EP - 1190
AU - Minoru FUJITA
AU - Yasushi KOBAYASHI
AU - Kenji SHIOZAWA
AU - Takahiko TAKAHASHI
AU - Fumio MIZUNO
AU - Hajime HAYAKAWA
AU - Makoto KATO
AU - Shigeki MORI
AU - Tetsuro KASE
AU - Minoru YAMADA
PY - 1993
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E76-C
IS - 7
JA - IEICE TRANSACTIONS on Electronics
Y1 - July 1993
AB - Digital neural networks are suitable for WSI implementation because their noise immunity is high, they have a fault tolerant structure, and the use of bus architecture can reduce the number of interconnections between neurons. To investigate the feasibility of WSIs, we integrated either 576 conventional neurons or 288 self-learning neurons on a 5-inch wafer, by using 0.8-µm CMOS technology and three metal layers. We also developed a new electron-beam direct-writing technology which enables easier fabrication of VLSI chips and wafer-level interconnections. We fabricated 288 self-learning neuron WSIs having as many as 230 good neurons.
ER -