IEICE TRANSACTIONS on Electronics
A 110-MHz/1-Mb Synchronous TagRAM
Summary :
A 4-way set associative TagRAM with 1.189-Mb capacity has been developed which can handle a secondary cache system of up to 16 Mbytes. A 9-ns cycle operation and clock to Dout of 4.7 ns are achieved by use of circuit techniques such as a pipelined decoding scheme, a single PMOS load BiCMOS main decoder, a BiCMOS sense-amplifying comparator, doubly placed self-timed write circuits, and highly linear VCO for a PLL. The device is successfully implemented with 0.7-µm double polysilicon double-metal BiCMOS technology.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E77-C No.5 pp.733-740
- Publication Date
- 1994/05/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))
- Category
Authors
Yasuo UNEKAWA
Tsuguo KOBAYASHI
Tsukasa SHIROTORI
Yukihiro FUJIMOTO
Takayoshi SHIMAZAWA
Kazutaka NOGAMI
Takehiko NAKAO
Kazuhiro SAWADA
Masataka MATSUI
Takayasu SAKURAI
Man Kit TANG
William A. HUFFMAN
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Yasuo UNEKAWA, Tsuguo KOBAYASHI, Tsukasa SHIROTORI, Yukihiro FUJIMOTO, Takayoshi SHIMAZAWA, Kazutaka NOGAMI, Takehiko NAKAO, Kazuhiro SAWADA, Masataka MATSUI, Takayasu SAKURAI, Man Kit TANG, William A. HUFFMAN, "A 110-MHz/1-Mb Synchronous TagRAM" in IEICE TRANSACTIONS on Electronics,
vol. E77-C, no. 5, pp. 733-740, May 1994, doi: .
Abstract: A 4-way set associative TagRAM with 1.189-Mb capacity has been developed which can handle a secondary cache system of up to 16 Mbytes. A 9-ns cycle operation and clock to Dout of 4.7 ns are achieved by use of circuit techniques such as a pipelined decoding scheme, a single PMOS load BiCMOS main decoder, a BiCMOS sense-amplifying comparator, doubly placed self-timed write circuits, and highly linear VCO for a PLL. The device is successfully implemented with 0.7-µm double polysilicon double-metal BiCMOS technology.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e77-c_5_733/_p
Copy
@ARTICLE{e77-c_5_733,
author={Yasuo UNEKAWA, Tsuguo KOBAYASHI, Tsukasa SHIROTORI, Yukihiro FUJIMOTO, Takayoshi SHIMAZAWA, Kazutaka NOGAMI, Takehiko NAKAO, Kazuhiro SAWADA, Masataka MATSUI, Takayasu SAKURAI, Man Kit TANG, William A. HUFFMAN, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 110-MHz/1-Mb Synchronous TagRAM},
year={1994},
volume={E77-C},
number={5},
pages={733-740},
abstract={A 4-way set associative TagRAM with 1.189-Mb capacity has been developed which can handle a secondary cache system of up to 16 Mbytes. A 9-ns cycle operation and clock to Dout of 4.7 ns are achieved by use of circuit techniques such as a pipelined decoding scheme, a single PMOS load BiCMOS main decoder, a BiCMOS sense-amplifying comparator, doubly placed self-timed write circuits, and highly linear VCO for a PLL. The device is successfully implemented with 0.7-µm double polysilicon double-metal BiCMOS technology.},
keywords={},
doi={},
ISSN={},
month={May},}
Copy
TY - JOUR
TI - A 110-MHz/1-Mb Synchronous TagRAM
T2 - IEICE TRANSACTIONS on Electronics
SP - 733
EP - 740
AU - Yasuo UNEKAWA
AU - Tsuguo KOBAYASHI
AU - Tsukasa SHIROTORI
AU - Yukihiro FUJIMOTO
AU - Takayoshi SHIMAZAWA
AU - Kazutaka NOGAMI
AU - Takehiko NAKAO
AU - Kazuhiro SAWADA
AU - Masataka MATSUI
AU - Takayasu SAKURAI
AU - Man Kit TANG
AU - William A. HUFFMAN
PY - 1994
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E77-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 1994
AB - A 4-way set associative TagRAM with 1.189-Mb capacity has been developed which can handle a secondary cache system of up to 16 Mbytes. A 9-ns cycle operation and clock to Dout of 4.7 ns are achieved by use of circuit techniques such as a pipelined decoding scheme, a single PMOS load BiCMOS main decoder, a BiCMOS sense-amplifying comparator, doubly placed self-timed write circuits, and highly linear VCO for a PLL. The device is successfully implemented with 0.7-µm double polysilicon double-metal BiCMOS technology.
ER -
English
