We analyzed the operation speed of the resonant tunneling logic gate, MOBILE, using a simple equivalent circuit model and varying parameters of I-V characteristics and capacitance of RTTs(resonant tunneling transistors). The switching time for large peak-to-valley(P/V)current ratios is smaller at small Vbmax(maximum bias voltage), but larger at large Vbmax than that for small P/V ratios in the case of present I-V characteristics with flat valley current. It is also demonstrated that the MOBILE operation fails if the bias voltage rises too fast, when the capacitance of the load and the driver is different due to the displacement current through the capacitance. These behaviors can be explained by considering the potential diagrams of the circuit.
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Yutaka OHNO, Shigeru KISHIMOTO, Takashi MIZUTANI, Koichi MAEZAWA, "Operation Speed Consideration of Resonant Tunneling Logic Gate Based on Circuit Simulation" in IEICE TRANSACTIONS on Electronics,
vol. E79-C, no. 11, pp. 1530-1536, November 1996, doi: .
Abstract: We analyzed the operation speed of the resonant tunneling logic gate, MOBILE, using a simple equivalent circuit model and varying parameters of I-V characteristics and capacitance of RTTs(resonant tunneling transistors). The switching time for large peak-to-valley(P/V)current ratios is smaller at small Vbmax(maximum bias voltage), but larger at large Vbmax than that for small P/V ratios in the case of present I-V characteristics with flat valley current. It is also demonstrated that the MOBILE operation fails if the bias voltage rises too fast, when the capacitance of the load and the driver is different due to the displacement current through the capacitance. These behaviors can be explained by considering the potential diagrams of the circuit.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e79-c_11_1530/_p
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@ARTICLE{e79-c_11_1530,
author={Yutaka OHNO, Shigeru KISHIMOTO, Takashi MIZUTANI, Koichi MAEZAWA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Operation Speed Consideration of Resonant Tunneling Logic Gate Based on Circuit Simulation},
year={1996},
volume={E79-C},
number={11},
pages={1530-1536},
abstract={We analyzed the operation speed of the resonant tunneling logic gate, MOBILE, using a simple equivalent circuit model and varying parameters of I-V characteristics and capacitance of RTTs(resonant tunneling transistors). The switching time for large peak-to-valley(P/V)current ratios is smaller at small Vbmax(maximum bias voltage), but larger at large Vbmax than that for small P/V ratios in the case of present I-V characteristics with flat valley current. It is also demonstrated that the MOBILE operation fails if the bias voltage rises too fast, when the capacitance of the load and the driver is different due to the displacement current through the capacitance. These behaviors can be explained by considering the potential diagrams of the circuit.},
keywords={},
doi={},
ISSN={},
month={November},}
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TY - JOUR
TI - Operation Speed Consideration of Resonant Tunneling Logic Gate Based on Circuit Simulation
T2 - IEICE TRANSACTIONS on Electronics
SP - 1530
EP - 1536
AU - Yutaka OHNO
AU - Shigeru KISHIMOTO
AU - Takashi MIZUTANI
AU - Koichi MAEZAWA
PY - 1996
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E79-C
IS - 11
JA - IEICE TRANSACTIONS on Electronics
Y1 - November 1996
AB - We analyzed the operation speed of the resonant tunneling logic gate, MOBILE, using a simple equivalent circuit model and varying parameters of I-V characteristics and capacitance of RTTs(resonant tunneling transistors). The switching time for large peak-to-valley(P/V)current ratios is smaller at small Vbmax(maximum bias voltage), but larger at large Vbmax than that for small P/V ratios in the case of present I-V characteristics with flat valley current. It is also demonstrated that the MOBILE operation fails if the bias voltage rises too fast, when the capacitance of the load and the driver is different due to the displacement current through the capacitance. These behaviors can be explained by considering the potential diagrams of the circuit.
ER -