Partitioned-Bus and Variable-Width-Bus Scheme for Low Power Digital Processors
Summary :
We propose a partitioned-bus architecture with a variable-width-bus scheme to reduce power consumption in bus lines in VLSIs. The partitioned-bus architecture (horizontal partitioning) restricts bus driving range to minimal, while the variable-width-bus scheme (vertical partitioning) uses additional tag lines so as to automatically indicate effective bus width with-out driving unnecessary bus lines depending on data to be transferred. Applying this method to a general purpose microprocessor, we demonstrate 30% and 35% power consumption reduction in bus lines, respectively for the partitioned-bus architecture and the variable-width-bus scheme, compared with the conventional bus architecture. Combining the both together, we show about 55% power consumption reduction in bus lines for typical applications. Increase in chip area for this architecture is about 30% compared with the conventional bus architecture.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E79-C No.3 pp.424-429
- Publication Date
- 1996/03/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- PAPER
- Category
- Electronic Circuits
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Makoto IKEDA, Kunihiro ASADA, "Partitioned-Bus and Variable-Width-Bus Scheme for Low Power Digital Processors" in IEICE TRANSACTIONS on Electronics,
vol. E79-C, no. 3, pp. 424-429, March 1996, doi: .
Abstract: We propose a partitioned-bus architecture with a variable-width-bus scheme to reduce power consumption in bus lines in VLSIs. The partitioned-bus architecture (horizontal partitioning) restricts bus driving range to minimal, while the variable-width-bus scheme (vertical partitioning) uses additional tag lines so as to automatically indicate effective bus width with-out driving unnecessary bus lines depending on data to be transferred. Applying this method to a general purpose microprocessor, we demonstrate 30% and 35% power consumption reduction in bus lines, respectively for the partitioned-bus architecture and the variable-width-bus scheme, compared with the conventional bus architecture. Combining the both together, we show about 55% power consumption reduction in bus lines for typical applications. Increase in chip area for this architecture is about 30% compared with the conventional bus architecture.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e79-c_3_424/_p
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@ARTICLE{e79-c_3_424,
author={Makoto IKEDA, Kunihiro ASADA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Partitioned-Bus and Variable-Width-Bus Scheme for Low Power Digital Processors},
year={1996},
volume={E79-C},
number={3},
pages={424-429},
abstract={We propose a partitioned-bus architecture with a variable-width-bus scheme to reduce power consumption in bus lines in VLSIs. The partitioned-bus architecture (horizontal partitioning) restricts bus driving range to minimal, while the variable-width-bus scheme (vertical partitioning) uses additional tag lines so as to automatically indicate effective bus width with-out driving unnecessary bus lines depending on data to be transferred. Applying this method to a general purpose microprocessor, we demonstrate 30% and 35% power consumption reduction in bus lines, respectively for the partitioned-bus architecture and the variable-width-bus scheme, compared with the conventional bus architecture. Combining the both together, we show about 55% power consumption reduction in bus lines for typical applications. Increase in chip area for this architecture is about 30% compared with the conventional bus architecture.},
keywords={},
doi={},
ISSN={},
month={March},}
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TY - JOUR
TI - Partitioned-Bus and Variable-Width-Bus Scheme for Low Power Digital Processors
T2 - IEICE TRANSACTIONS on Electronics
SP - 424
EP - 429
AU - Makoto IKEDA
AU - Kunihiro ASADA
PY - 1996
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E79-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 1996
AB - We propose a partitioned-bus architecture with a variable-width-bus scheme to reduce power consumption in bus lines in VLSIs. The partitioned-bus architecture (horizontal partitioning) restricts bus driving range to minimal, while the variable-width-bus scheme (vertical partitioning) uses additional tag lines so as to automatically indicate effective bus width with-out driving unnecessary bus lines depending on data to be transferred. Applying this method to a general purpose microprocessor, we demonstrate 30% and 35% power consumption reduction in bus lines, respectively for the partitioned-bus architecture and the variable-width-bus scheme, compared with the conventional bus architecture. Combining the both together, we show about 55% power consumption reduction in bus lines for typical applications. Increase in chip area for this architecture is about 30% compared with the conventional bus architecture.
ER -
English
