The realization of scientific manufacturing of ULSIs in the 21st century will require the development of a technical infrastructure of "Ultra Clean Technology" and the firm establishment of the three principles of high performance processes. Three principles are 1)Ultra Clean Si Wafer Surface, 2)Ultra Clean Processing Environment, and 3)Perfect Parameter controlled process. This paper describes the methods of resolving the problems inherent in Ultra Clean Technology, taking as examples issues in quarter-micron or more advanced semiconductor process and manufacturing equipment, particularly when faced with the challenges of plasma dry etching. Issues indispensable to the development of tomorrow's highly accurate and reliable plasma dry etching equipment are the development of technologies for the accurate measurement of plasma parameters, ultra clean gas delivery systems, chamber cleaning technology on an in-situ basis, and simulating the plasma chemistry.This paper also discusses the standardization of semiconductor manufacturing equipment, which is considered one of the ways to reduce the steep rise in production line construction costs. The establishment of Ultra Clean Technology also plays a vital role in this regard.

The scaling laws between the design rules and the smallest sizes and numbers of particles capable of causing pattern defects and scrapping dies in semiconductor device manufacturing are described. Simulation with electromagnetic waveguide model indicates the possibility that particles, the sizes of which are of comparable order or even smaller than the wavelength of the lithography irradiation sources, are capable of causing pattern defects. For example, in the future 0.25 µm-design-rule era, the critical sizes of Si, Al, and SiO₂ particles are simulated as 120 nm 120 nm, 120 nm 120 nm, and 560 nm 560 nm, respectively, in the case of 0.7 µm-thick chemically-amplified positive photoresist with 47 nm-thick top anti-reflective coating films. Future giga-scale integration era is also predicted.

A detabase system that provides step-by-step guidance for LSI failure analysts has been developed. This system has three main functions: database, navigator, and chip tracking. The datebase stores failure analysis information such as analysis method and failure mechanisms including image data. It also stores conditions and results of each analysis step and decisions to proceeds to the next analysis step. With 2000 failure analysis cases, data retrieval takes 6.6 seconds, a table containing 20 photos is presented in 6.5 seconds, and a different set of data can be displayed in 0.6 seconds. The navigator displays a standard analysis procedure illustrated in flow charts.The chip tracking shows where the particular chip is and what analysis it is undergoing, which is useful for the situation where many chips are simultaneously analyzed. Thus, this system has good enough functions of analysis procedure management and performance of quick data access to make failure analysis easier and more successful.

A new yield prediction model has been developed, which can successfully describe the actual chip fabrication yield. It basically consists of modeling of particles deposited on wafer surface, considering the change in their size and spatial distribution due to the subsequent processing steps and a new concept of virtual line width in pattern layouts. It is confirmed that this yield prediction model serves as an effective navigator for improvement/optimization of fabrication lines such as pointing out the process step/equipments to be modified for yield improvements.

A unified process flow management system (UPFMS) that combines a CIM system, process/device simulator, CAD system, and manufacturing line schedular has been developed. This new system uses a new language called PDL to describe the process flow as common information for all systems. The UPFMS consists of the flow edit section, the flow inspection section, and several types of interface programs to make it suitable for use with other systems. The process flow data described using the PDL in the UPFMS provides data for controlling lots in CIM system. If modification of the process flow data in the CIM system is required, the process flow data is returned to the UPFMS and modified with inspection using a knowledge data base. Then, the error-free process flow data is sent back to the CIM system for Processes after flow inspection. Moreover, the UPFMS, with the new language PDL, generates recipe data for the equipment using an interface program, and recipe data is input to several types of equipment. Furthermore, the PDL process flow data can also be used as input data for the manufacturing line scheduler using another interface program. Mask and layout data in a CAD system can be exchanged among process/device simulators by using the UPFMS, and thus two-dimensional device characteristics. Spice paramenters can be also to be created. The UPFMS combines with CIM system, process/device simulator, CAD system, and the manufacturing line scheduler using common information, PDL. The process flow data created in the UPFMS can be used to control all systems from the simulation to CIM system as common data.

A new line simulator, SEMALIS has been developed. This simulator can handle complicated lot processings to maintain processing quality and efficient line operations to improve line performance. The current manufacturing line consists of five resource models: lot, process sequence, equipment, lot processing, and line operations. The parameters of these models are defined so as to accurately reflect the state of the line operations. From our simulation results, we confirmed that SEMALIS accurately identifies bottlenecks or starvations where equipment can be added or reduced to optimize equipment utilization through resource planning, and that SEMALIS can also be used to evaluate the long-term effects of line operating methods on the line performance of ASIC manufacturing lines.

A new cost model CPO (Cost of Process Ownership) has been proposed. We have already the well known cost model CEO (Cost of Equipment Ownership) [1] which is a cost index assigned independently to individual equipment. However, CPO is basically a cost index assigned to process step in processing flow chart of actual product in a Fab line. Therefore, it is essentially more effective to evaluate the Fab performance such as cost analysis of process steps, estimation of the whole wafer processing cost for specific product, identification of the bottle neck process step or equipment in a Fab line. Further, in designing a high cost-performance factory or in modifying existing factory, it affords important guide such as optimal scales for both factory and equipments with their investment efficiency.

Systems for removing particulates and gaseous contaminants using the UV/photoelectron method under atmospheric and low pressure conditions have been investigated and its availability has been demonstrated. From experimental results, more than 90 % of particulate contaminants are removed by this method under atomospheric and low pressure conditions. This method can be used to design superclean spaces for wafer stockers, and wafer delivering systems in the LSI fabrication process.

In order to simulate the mechanism of particle growth by film deposition, imaginary-particle formation method has been newly developed. By using this formation method, the particle size, the particle height and the position of particle on a wafer could be controlled very easily. In this study, the imaginary-particles of various size larger than 0.15 micron and various height were formed on a wafer. By using these imaginary-particles, the effects of a deposition method, a film thickness, a particle size and a particle height upon the particle growth were investigated. As deposition methods, low pressure CVD method, plasma CVD method and sputtering method were compared. As a result, in all deposition method, it's clear that the particle growth doesn't depend on the initial size, and is proportional to the film thickness. Their particle growth rates are characterized by the deposition method, and their values are 1.9, 1.1 and 0.64 in low pressure CVD, plasma CVD and sputtering method, respectively. These values can be explained by the step coverage decided by the deposition method. Furthermore, the particle growth on imaginary-particle was compared with that on the real-particle. It is clear that the growth mechanism of the real-particle is closely similar to that of imaginary-particle, and the study by use of the imaginary-particle is very effective to make clear the mechanism of particle growth. Therefore, the particle size which should be controlled before deposition process is necessary to be decided by counting the particle growth shown in this paper.

A new electron-beam wafer inspection system has been developed. The system has a resolution of 5 nm or better, and is applicable to quarter-micron devices such as 256 Mbit DRAMs. The most remarkable feature of this system is that a specimen stage is built in the objective lens and allows a working distance (WD) of 0. "WD=0"minimizes the effect of lens aberrations, and maximizes the resolving power. Innovative designs to achieve WD=0 are as follows: (1)A large objective lens of 730-mm width 730-mm depth 620-mm height that serves as a specimen chamber, has been developed. (2)A hollow specimen stage made of non-magnetic materials has been developed.It allows the lower pole piece and magnetic coile of the objective lens inside it. (3)Acoustic motors made of non-magnetic materials are em-ployed for use in vacuum.

A new observation technique for process-induced micro-defects in ULSI using a combination of anodic oxidation and chemical removal of the oxide has been developed. Enhanced oxidation has occurred at the defect region due to the stress field and then craterlike delineation has been formed after oxide removal. AFM and SEM observation of the micro-defects induced by ion implantation and applications using this tech-nique to the failure analysis of MOS device fabrication are presented.

A new anti-static technology to neutralize static electricity by high energy photon irradiation has been developed. Ions and electrons required for neutralization are generated by ionization of gas molecules in the vicinity of a charged substance. Gas molecules absorbs photons to become ionized. The wavelength chosen for the irradiation depends on the neutralization atmosphere. Soft X-rays with wavelength over about 1 are effective in air or O₂ gas at pressure higher than several hundreds Torr. Vacuum UV-rays with wavelength below about 1350 is effective in N₂ gas, Ar gas, or reduced pressure ambients. These methods feature excellent neutralization capa-bility. Electrostatic potential can be reduced to 0 V in a very short time without encountering the problems of which conven-tional corona discharge ionizers.

Wet cleaning in actual LSI process is difficult to remove contamination perfectly, because the cleaning condition must be moderate to maintain device characteristics and device texture and because wet cleaning is not so effective for the particles generated during processes such as etching, photo lithography and film formation. Particle reduction depends on particle characteristics, i.e. the sticking force and the chemical structure of the particles. Metallic contamination on wafers, depending on the kind of solutions and the metal concentration in cleaning solutions, degrades TDDB characteristics and recom-bination lifetime. Although the lifetime degradation by the metallic contamination is appreciable, it is much smaller than those caused by damage in etching and in ion implantation.

In order to establish the advanced and costeffective wet cleaning technology, it is essential to reveal the mechanism of contamination adhesion and removal on Si surfaces in solutions. To reveal the mechanism of noble metal adhesion onto the Si surface in wet processes, the behavior of Cu²⁺ deposition onto Si surfaces in solutions was investigated. The experimental results reveal the mechanism of electrochemical metallic contamination of noble metals on Si surfaces. Moreover, it was found that, in HF solutions, Si is not directly etched in a form of SiF₆^2- by such an oxidizing agent as Cu²⁺ but is first turned to oxide and then etched off. For preventing noble metal deposition on Si surfaces, it is necessary not only to keep the noble metals in the solution (i.e. to dissolve noble metals) but also to prevent oxidation/reduction reaction between Si and the noble metal ion. It is found that this oxidation/reduction reaction can be prevented by increasing the redox potential of solutions, injecting surfactants or chelating agents, and making the Si surface covered with oxide. It has been revealed that Cu deposition can be prevented by setting the redox potential of the solution at over 0.75 V vs. NHE. Cu deposition in DHF solutions can be prevented by setting the redox potential at 0.85 V vs. NHE or more. For removing Cu from the Si surface, the same conditions are found to be necessary. Moreover, it is revealed that metallic impurities included in the oxide can be removed only by etching. It is also revealed that chemicals to prevent metal deposition must be used to remove metals such as Cu which easily get redeposited on the bare Si surface. Finally, a new wet cleaning process employing ozonized ultrapure water, NH₄OH/H₂O₂/H₂O, and surfactant-injected DHF to replace the conventional RCA cleaning method is proposed.

A regeneration technology of fluorite (CaF₂) from spent HF and Buffered HF (BHF) has been investigated. The mechanism of "direct conversion" of granular calcite (CaCO₃) into granular fluorite has revealed and several special phenomena are first found to be efficient. An advanced system has been developed. This system regenerates granular fluorite by conversion of granular calcite filled in a column. High purity and low water fluorite is recovered as a substitute for natural fluorspar (CaF₂). The fluorine concentration in the processed effluent is minimized to a level of 5 ppm. The separation of the HF processing line and BHF processing line equipped ammonia stripper is an important to system design because ammonia generated from BHF significantly retards the conversion efficiency from CaCO₃ to CaF₂. The new system reforming the conventional slaked lime processing solves long-pending problem, resulting in a very compact system with a very small amount of product.

High-performance ULSI devices require ultraclean silicon surfaces, the complete removal of native oxides, and atomic level flatness and stabilization of the cleaned surfaces against molecular contaminants. Dry cleaning techniques are an attractive alternative to conventional wet processing for future ULSI production using cluster chambers or multi-process cham-bers. Organic contaminants, including photoresist polymers, are effectively removed by photo-excited ozone cleaning. We have found photo-excited halogen radicals to be useful for removing trace metals and native oxides from silicon surfaces without damaging on silicon and silicon-dioxide surfaces. We success-fully terminated hydrogen on (100) silicon surfaces by annealing in pure hydrogen ambient. A dry cleaning system with these sequential processes will be useful in constructing fully-integrated mass-production lines of high-performance ULSI devices.

A novel method has been developed to improve the dry etching selectivity of aluminum alloy with respect to photoresist by implanting ions into the patterned photoresist. The selectivity becomes 7.5, which is 5 times higher than that of the unimplanted case. Accordingly, this technology is very promising for fabricating multi-level interconnections in sub-half micron LSIs.

We have developed a complete chromium oxide (Cr₂O₃) passivated gas tubing system by introducing ferritic stainless steel instead of conventional austenitic stainless steel (SUS316L). 100% Cr₂O₃ passivation film can be formed on electropolished ferritic stainless steel surface because the diffusion coefficient of Cr in ferritic stainless steel is 10⁴ times larger than in austenitic stainless steel. In ferritic stainless steel, moreover, welded bead surface is covered by 100% Cr₂O₃ pas-sivated film by an introduction of advanced welding technology.

We studied effects of 50-200-keV electrons on semiconductor devices using BEASTLI (backscattered electron assisting LSI inspection) method. When irradiating semiconduc-tor devices with such high-energy electrons, we have to note two phenomena. The first is surface charging and the second is device damage. In our study of surface charging, we found that a net positive charge was formed on the device surface. The positive surface charges do not cause serious influence for observation so that we can inspect wafers without problems. The positive surface charging may be brought about because most incident electrons penetrate the device layer and reach the conducting substrate of the semiconductor device. For the device damage, we studied MOS devices which were sensitive to electron-beam irradiation. By applying a 400- annealing to electron-beam irradiated MOS devices, we could restore the initial characteris-tics of MOS devices. However, in order to recover hot-carrier degradation due to neutral traps, we had to apply a 900- annealing to the electron-beam irradiated MOS devices. Thus, BEASTLI could be successfully used by providing an apporopri-ate annealing to the electron-beam irradiated MOS devices.

It has been revealed that ion bombardment energy and ion flux density play an essentially critical role in SiN_x deposition process of PECVD in TFT-LCD production. Ion energy and ion flux density bombarding onto substrate surface are known to be extracted from waveform of RF applied to an electrode. Using this method, we investigated film quality of SiN_x formed in the conventional parallel plate PECVD equipment. When N₂ + H₂ or N₂ + Ar is employed as a carrier gas in source gas (SiH₄ + NH₃), we have defined normalized ion flux density as ion flux density divided by deposited SiN_x molecule which must be increased to obtain high quality SiN_x film while ion energy is suppressed at low level as not giving damages on the film surface. This technique has made it possible to securely form SiN_x film (2500 ) featuring dielectric break-down field intensity of 8.5 MV/cm at 250 on a glass substrate with Cr gate interconnects of 1000 having vertical step struc-ture. One of the important factors to improve film quality of SiN_x deposited in PECVD is to increase ion flux density while keeping ion bombardment energy low enough to protect growing surface against any damages. Using this technique inverse-staggered TFT-array featuring field effect mobility of 0.96 cm²/V・s has been demonstrated which gate insulator SiN_x, non-doped a-Si: H and a-Si: H(n⁺) were formed continuously at the identical substrate temperature of 250.

In order to reduce the ever increasing cost for ULSI manufacturing due to the complexity of integrated circuits, dramatic simplification in the logic LSI architecture as well as the very flexible circuit configuration have been achieved using a highfunctionality device neuron-MOSFET (γMOS).In γMOS logic circuits, however, computations based on the multiple-valued logic is the key for enhancing the functionality. Therefore, much higher accuracy of processing is required. After brief description of the operational principle of γMOS logic, the relationship between the number of multiple logic levels and the functionality enhancement is discussed for further enhancing the functionality of γMOS logic circuits by increasing the number of multiple logic levels, and the accuracy requirements for the manufacturing processes are studied. The order of a few percent accuracy is required for all principal device structural parameters when it is aimed to handle 50-level multiple-valued variable in the γMOS logic circuit.

A novel redundancy method suitable for an ultra-high-speed SRAM with logic gates is proposed. Fuse decoders are used to reduce the number of fuses, thus suppressing the access time degradation. This makes it possible to flip chip bond an SRAM with logic gates, which has a high pin count and operates at a very high frequency. To combine the new redundancy method and an ECL decoder circuit with a BiCMOS inverter, several schemes for disabling a defective cell and enabling a spare one are discussed. A 1-Mb ECL-CMOS SRAM with 120-k logic gates was fabricated using 0.3-µm BiCMOS technology. This SRAM consists of 16 RAM macros, and the RAM macro had an access time of only 0.65 ns. The access time degradation after repair was less than 50 ps.

We propose a partitioned-bus architecture with a variable-width-bus scheme to reduce power consumption in bus lines in VLSIs. The partitioned-bus architecture (horizontal partitioning) restricts bus driving range to minimal, while the variable-width-bus scheme (vertical partitioning) uses additional tag lines so as to automatically indicate effective bus width with-out driving unnecessary bus lines depending on data to be transferred. Applying this method to a general purpose microprocessor, we demonstrate 30% and 35% power consumption reduction in bus lines, respectively for the partitioned-bus architecture and the variable-width-bus scheme, compared with the conventional bus architecture. Combining the both together, we show about 55% power consumption reduction in bus lines for typical applications. Increase in chip area for this architecture is about 30% compared with the conventional bus architecture.

High-frequency capacitance-voltage (C-V) characteristics of buried-channel MOS capacitors with a structure of subquarter-micron pMOS have been measured and analyzed, emphasizing transient behavior. The C-V characteristics, including transient behavior, of buried-channel MOS capacitors that have a counter-doped p layer at the surface of n substrate are very similar to those of surface-channel MOS capacitors of n substrate if the counter-doped layer is shallow enough to be fully inverted at large positive bias. As gate voltage is decreased, equilibrium capacitance for inversion (accumulation for the counter-doped layer) reaches a minimum value and then slightly increases to saturate, which is peculiar to buried-channel capacitors. The gate voltage for minimum capacitance, which has been used to estimate the threshold voltage, changes dramatically by illumination even in room light. Net doping profiles of n-type dopant can be obtained from pulsed C-V characteristics even for buried-channel capacitors. For MOS capacitors with thinner gate oxide (5 nm), steady-state C-V curve is not an equilibrium one but a deep depletion one at room temperature. This is because holes are drained away by tunneling through the thin gate oxide.

We have proposed a multiplexed fiber-optic sensor system using an optical loop with a frequency shifter. The measured output power spectrum of the system has shown that the multiprexed signals superimpose upon a noise pedestal which is like a series of hill peaks. In this paper, the output power spectrum is theoretically analyzed from the output intensity autocor-relation function. It displays that the noise pedestal originates from the laser phase-induced intensity noise. The noise level depends on the coherence time of the laser source. The positions of peaks are decided by the working frequency of the frequency shifter in the optical loop. The sensitivity of the system are related to the bandwidth B, the coherence time T_c, the sensor number n to be multiplexed, the loop loss α, and the fiber coupler parameters. Properly choosing these parameters is beneficial to improve the sensitivity of system.

An efficient full-wave approach for the accurate characterization of a H-plane waveguide π-junction with an inductive post and a waveguide cross-junction is proposed. By employing the port reflection coefficient method (PRCM), the analysis and solution procedures of these complex waveguide junctions are greatly simplified and only the calculation of field reflections caused by the simplest waveguide step-junction discontinuities are required. The reflections are easily determined by the mode-matching technique. Scattering parameters of these junctions are provided and discussed in terms of the working frequency and the geometrical dimensions of the junctions. Calculated results are compared with those of other papers and measurements, all show good agreement.