Capacitance-Voltage Characteristics of Buried-Channel MOS Capacitors with a Structure of Subquarter-Micron pMOS

Masayasu MIYAKE; Yukio OKAZAKI

Capacitance-Voltage Characteristics of Buried-Channel MOS Capacitors with a Structure of Subquarter-Micron pMOS

Masayasu MIYAKE, Yukio OKAZAKI

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High-frequency capacitance-voltage (C-V) characteristics of buried-channel MOS capacitors with a structure of subquarter-micron pMOS have been measured and analyzed, emphasizing transient behavior. The C-V characteristics, including transient behavior, of buried-channel MOS capacitors that have a counter-doped p layer at the surface of n substrate are very similar to those of surface-channel MOS capacitors of n substrate if the counter-doped layer is shallow enough to be fully inverted at large positive bias. As gate voltage is decreased, equilibrium capacitance for inversion (accumulation for the counter-doped layer) reaches a minimum value and then slightly increases to saturate, which is peculiar to buried-channel capacitors. The gate voltage for minimum capacitance, which has been used to estimate the threshold voltage, changes dramatically by illumination even in room light. Net doping profiles of n-type dopant can be obtained from pulsed C-V characteristics even for buried-channel capacitors. For MOS capacitors with thinner gate oxide (5 nm), steady-state C-V curve is not an equilibrium one but a deep depletion one at room temperature. This is because holes are drained away by tunneling through the thin gate oxide.

Publication: IEICE TRANSACTIONS on Electronics Vol.E79-C No.3 pp.430-436

Publication Date: 1996/03/25

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Type of Manuscript: PAPER

Category: Semiconductor Materials and Devices

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Masayasu MIYAKE, Yukio OKAZAKI, "Capacitance-Voltage Characteristics of Buried-Channel MOS Capacitors with a Structure of Subquarter-Micron pMOS" in IEICE TRANSACTIONS on Electronics, vol. E79-C, no. 3, pp. 430-436, March 1996, doi: .
Abstract: High-frequency capacitance-voltage (C-V) characteristics of buried-channel MOS capacitors with a structure of subquarter-micron pMOS have been measured and analyzed, emphasizing transient behavior. The C-V characteristics, including transient behavior, of buried-channel MOS capacitors that have a counter-doped p layer at the surface of n substrate are very similar to those of surface-channel MOS capacitors of n substrate if the counter-doped layer is shallow enough to be fully inverted at large positive bias. As gate voltage is decreased, equilibrium capacitance for inversion (accumulation for the counter-doped layer) reaches a minimum value and then slightly increases to saturate, which is peculiar to buried-channel capacitors. The gate voltage for minimum capacitance, which has been used to estimate the threshold voltage, changes dramatically by illumination even in room light. Net doping profiles of n-type dopant can be obtained from pulsed C-V characteristics even for buried-channel capacitors. For MOS capacitors with thinner gate oxide (5 nm), steady-state C-V curve is not an equilibrium one but a deep depletion one at room temperature. This is because holes are drained away by tunneling through the thin gate oxide.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e79-c_3_430/_p

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@ARTICLE{e79-c_3_430,
author={Masayasu MIYAKE, Yukio OKAZAKI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Capacitance-Voltage Characteristics of Buried-Channel MOS Capacitors with a Structure of Subquarter-Micron pMOS},
year={1996},
volume={E79-C},
number={3},
pages={430-436},
abstract={High-frequency capacitance-voltage (C-V) characteristics of buried-channel MOS capacitors with a structure of subquarter-micron pMOS have been measured and analyzed, emphasizing transient behavior. The C-V characteristics, including transient behavior, of buried-channel MOS capacitors that have a counter-doped p layer at the surface of n substrate are very similar to those of surface-channel MOS capacitors of n substrate if the counter-doped layer is shallow enough to be fully inverted at large positive bias. As gate voltage is decreased, equilibrium capacitance for inversion (accumulation for the counter-doped layer) reaches a minimum value and then slightly increases to saturate, which is peculiar to buried-channel capacitors. The gate voltage for minimum capacitance, which has been used to estimate the threshold voltage, changes dramatically by illumination even in room light. Net doping profiles of n-type dopant can be obtained from pulsed C-V characteristics even for buried-channel capacitors. For MOS capacitors with thinner gate oxide (5 nm), steady-state C-V curve is not an equilibrium one but a deep depletion one at room temperature. This is because holes are drained away by tunneling through the thin gate oxide.},
keywords={},
doi={},
ISSN={},
month={March},}

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TY - JOUR
TI - Capacitance-Voltage Characteristics of Buried-Channel MOS Capacitors with a Structure of Subquarter-Micron pMOS
T2 - IEICE TRANSACTIONS on Electronics
SP - 430
EP - 436
AU - Masayasu MIYAKE
AU - Yukio OKAZAKI
PY - 1996
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E79-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 1996
AB - High-frequency capacitance-voltage (C-V) characteristics of buried-channel MOS capacitors with a structure of subquarter-micron pMOS have been measured and analyzed, emphasizing transient behavior. The C-V characteristics, including transient behavior, of buried-channel MOS capacitors that have a counter-doped p layer at the surface of n substrate are very similar to those of surface-channel MOS capacitors of n substrate if the counter-doped layer is shallow enough to be fully inverted at large positive bias. As gate voltage is decreased, equilibrium capacitance for inversion (accumulation for the counter-doped layer) reaches a minimum value and then slightly increases to saturate, which is peculiar to buried-channel capacitors. The gate voltage for minimum capacitance, which has been used to estimate the threshold voltage, changes dramatically by illumination even in room light. Net doping profiles of n-type dopant can be obtained from pulsed C-V characteristics even for buried-channel capacitors. For MOS capacitors with thinner gate oxide (5 nm), steady-state C-V curve is not an equilibrium one but a deep depletion one at room temperature. This is because holes are drained away by tunneling through the thin gate oxide.
ER -