IEICE TRANSACTIONS on Electronics
Capacitance Coupling Immune, Transient Sensitive Accelerator for Resistive Interconnect Signals of Subquarter Micron ULSI
Summary :
This paper presents a new circuit scheme called a transient sensitive accelerator(TSA) circuit for highly resistive interconnects. The TSA can reduce both delay time and crosstalk voltage. Using the TSA with an interconnect length of 30 mm reduces delay time and crosstalk voltage by 29% and 20%, respectively, A further advantage is that the TSA operates in self-time and thus can be applied to bidirectional signal communication.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E79-C No.7 pp.942-947
- Publication Date
- 1996/07/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on the 1995 Symposium on VLSI Circuits (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.31, No.4 April 1996))
- Category
- Interface Circuits
Authors
Keyword
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Tomofumi IIMA, Masayuki MIZUNO, Tadahiko HORIUCHI, Masakazu YAMASHINA, "Capacitance Coupling Immune, Transient Sensitive Accelerator for Resistive Interconnect Signals of Subquarter Micron ULSI" in IEICE TRANSACTIONS on Electronics,
vol. E79-C, no. 7, pp. 942-947, July 1996, doi: .
Abstract: This paper presents a new circuit scheme called a transient sensitive accelerator(TSA) circuit for highly resistive interconnects. The TSA can reduce both delay time and crosstalk voltage. Using the TSA with an interconnect length of 30 mm reduces delay time and crosstalk voltage by 29% and 20%, respectively, A further advantage is that the TSA operates in self-time and thus can be applied to bidirectional signal communication.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e79-c_7_942/_p
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@ARTICLE{e79-c_7_942,
author={Tomofumi IIMA, Masayuki MIZUNO, Tadahiko HORIUCHI, Masakazu YAMASHINA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Capacitance Coupling Immune, Transient Sensitive Accelerator for Resistive Interconnect Signals of Subquarter Micron ULSI},
year={1996},
volume={E79-C},
number={7},
pages={942-947},
abstract={This paper presents a new circuit scheme called a transient sensitive accelerator(TSA) circuit for highly resistive interconnects. The TSA can reduce both delay time and crosstalk voltage. Using the TSA with an interconnect length of 30 mm reduces delay time and crosstalk voltage by 29% and 20%, respectively, A further advantage is that the TSA operates in self-time and thus can be applied to bidirectional signal communication.},
keywords={},
doi={},
ISSN={},
month={July},}
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TY - JOUR
TI - Capacitance Coupling Immune, Transient Sensitive Accelerator for Resistive Interconnect Signals of Subquarter Micron ULSI
T2 - IEICE TRANSACTIONS on Electronics
SP - 942
EP - 947
AU - Tomofumi IIMA
AU - Masayuki MIZUNO
AU - Tadahiko HORIUCHI
AU - Masakazu YAMASHINA
PY - 1996
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E79-C
IS - 7
JA - IEICE TRANSACTIONS on Electronics
Y1 - July 1996
AB - This paper presents a new circuit scheme called a transient sensitive accelerator(TSA) circuit for highly resistive interconnects. The TSA can reduce both delay time and crosstalk voltage. Using the TSA with an interconnect length of 30 mm reduces delay time and crosstalk voltage by 29% and 20%, respectively, A further advantage is that the TSA operates in self-time and thus can be applied to bidirectional signal communication.
ER -
English
