Current Sense Amplifiers for Low-Voltage Memories
Summary :
The principles and design of current sense amplifiers for low-voltage MOS memories are described. The low input impedance of current sense amplifiers is explained using a simple model consisting of negative and positive resistance. A description of the model realized by a common-gate MOS amplifier employing transconductance enhancing techniques is also given. Some current sensing schemes for low-voltage ROM's and/or SRAM's are shown. For SRAM application, a current sensing scheme employing large-gain inverter-type amplifiers is proposed. A test chip including SRAM macrocells was designed and fabricated with 3.3-V 0.5-µm CMOS technology. An SRAM using current sense amplifiers was able to demonstrate that current sensing suppressed bitline delay to half that in conventional current-mirror types. The current sense amplifier had the same operating limit as the current-mirror type for low supply voltages. The measured operating limit of the STSM in this work was 1.3-V for threshold voltages of 0.55-V(n-channel) and -0.65-V(p-channel).
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E79-C No.8 pp.1120-1130
- Publication Date
- 1996/08/25
- Publicized
- Online ISSN
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- Type of Manuscript
- PAPER
- Category
- Integrated Electronics
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Nobutaro SHIBATA, "Current Sense Amplifiers for Low-Voltage Memories" in IEICE TRANSACTIONS on Electronics,
vol. E79-C, no. 8, pp. 1120-1130, August 1996, doi: .
Abstract: The principles and design of current sense amplifiers for low-voltage MOS memories are described. The low input impedance of current sense amplifiers is explained using a simple model consisting of negative and positive resistance. A description of the model realized by a common-gate MOS amplifier employing transconductance enhancing techniques is also given. Some current sensing schemes for low-voltage ROM's and/or SRAM's are shown. For SRAM application, a current sensing scheme employing large-gain inverter-type amplifiers is proposed. A test chip including SRAM macrocells was designed and fabricated with 3.3-V 0.5-µm CMOS technology. An SRAM using current sense amplifiers was able to demonstrate that current sensing suppressed bitline delay to half that in conventional current-mirror types. The current sense amplifier had the same operating limit as the current-mirror type for low supply voltages. The measured operating limit of the STSM in this work was 1.3-V for threshold voltages of 0.55-V(n-channel) and -0.65-V(p-channel).
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e79-c_8_1120/_p
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@ARTICLE{e79-c_8_1120,
author={Nobutaro SHIBATA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Current Sense Amplifiers for Low-Voltage Memories},
year={1996},
volume={E79-C},
number={8},
pages={1120-1130},
abstract={The principles and design of current sense amplifiers for low-voltage MOS memories are described. The low input impedance of current sense amplifiers is explained using a simple model consisting of negative and positive resistance. A description of the model realized by a common-gate MOS amplifier employing transconductance enhancing techniques is also given. Some current sensing schemes for low-voltage ROM's and/or SRAM's are shown. For SRAM application, a current sensing scheme employing large-gain inverter-type amplifiers is proposed. A test chip including SRAM macrocells was designed and fabricated with 3.3-V 0.5-µm CMOS technology. An SRAM using current sense amplifiers was able to demonstrate that current sensing suppressed bitline delay to half that in conventional current-mirror types. The current sense amplifier had the same operating limit as the current-mirror type for low supply voltages. The measured operating limit of the STSM in this work was 1.3-V for threshold voltages of 0.55-V(n-channel) and -0.65-V(p-channel).},
keywords={},
doi={},
ISSN={},
month={August},}
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TY - JOUR
TI - Current Sense Amplifiers for Low-Voltage Memories
T2 - IEICE TRANSACTIONS on Electronics
SP - 1120
EP - 1130
AU - Nobutaro SHIBATA
PY - 1996
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E79-C
IS - 8
JA - IEICE TRANSACTIONS on Electronics
Y1 - August 1996
AB - The principles and design of current sense amplifiers for low-voltage MOS memories are described. The low input impedance of current sense amplifiers is explained using a simple model consisting of negative and positive resistance. A description of the model realized by a common-gate MOS amplifier employing transconductance enhancing techniques is also given. Some current sensing schemes for low-voltage ROM's and/or SRAM's are shown. For SRAM application, a current sensing scheme employing large-gain inverter-type amplifiers is proposed. A test chip including SRAM macrocells was designed and fabricated with 3.3-V 0.5-µm CMOS technology. An SRAM using current sense amplifiers was able to demonstrate that current sensing suppressed bitline delay to half that in conventional current-mirror types. The current sense amplifier had the same operating limit as the current-mirror type for low supply voltages. The measured operating limit of the STSM in this work was 1.3-V for threshold voltages of 0.55-V(n-channel) and -0.65-V(p-channel).
ER -
English
