Low-Power Circuit Design Techniques for Si Bipolar Gbit/s LSIs
An Overview
Summary :
This paper surveys low-power design techniques for Si bipolar Gbit/s LSIs. First, a total strategy for power reduction in bipolar LSIs is described. The power dissipation of Si bipolar LSIs can be minimized by reducing the supply voltage, switching and driving currents, the power of input and output circuits, and the equivalent "on" ratio. Widely spread activities from device to architecture levels are indispensable and each of the low-power techniques reduces power by a factor of about 0.5 to 0.7. The integration of these techniques is very important, and as a certain example of their effectiveness, an SOH signal processing LSI is demonstrated with a reduction factor of 1/10. Comparisons with other device technologies for low power characteristics reveal the low-power potential of bipolar LSIs in the Gbit/s region.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E80-C No.12 pp.1511-1522
- Publication Date
- 1997/12/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section INVITED PAPER (Special Issue on Low-Power and High-Speed LSI Technologies)
- Category
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Haruhiko ICHINO, "Low-Power Circuit Design Techniques for Si Bipolar Gbit/s LSIsAn Overview" in IEICE TRANSACTIONS on Electronics,
vol. E80-C, no. 12, pp. 1511-1522, December 1997, doi: .
Abstract: This paper surveys low-power design techniques for Si bipolar Gbit/s LSIs. First, a total strategy for power reduction in bipolar LSIs is described. The power dissipation of Si bipolar LSIs can be minimized by reducing the supply voltage, switching and driving currents, the power of input and output circuits, and the equivalent "on" ratio. Widely spread activities from device to architecture levels are indispensable and each of the low-power techniques reduces power by a factor of about 0.5 to 0.7. The integration of these techniques is very important, and as a certain example of their effectiveness, an SOH signal processing LSI is demonstrated with a reduction factor of 1/10. Comparisons with other device technologies for low power characteristics reveal the low-power potential of bipolar LSIs in the Gbit/s region.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e80-c_12_1511/_p
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@ARTICLE{e80-c_12_1511,
author={Haruhiko ICHINO, },
journal={IEICE TRANSACTIONS on Electronics},
title={Low-Power Circuit Design Techniques for Si Bipolar Gbit/s LSIsAn Overview},
year={1997},
volume={E80-C},
number={12},
pages={1511-1522},
abstract={This paper surveys low-power design techniques for Si bipolar Gbit/s LSIs. First, a total strategy for power reduction in bipolar LSIs is described. The power dissipation of Si bipolar LSIs can be minimized by reducing the supply voltage, switching and driving currents, the power of input and output circuits, and the equivalent "on" ratio. Widely spread activities from device to architecture levels are indispensable and each of the low-power techniques reduces power by a factor of about 0.5 to 0.7. The integration of these techniques is very important, and as a certain example of their effectiveness, an SOH signal processing LSI is demonstrated with a reduction factor of 1/10. Comparisons with other device technologies for low power characteristics reveal the low-power potential of bipolar LSIs in the Gbit/s region.},
keywords={},
doi={},
ISSN={},
month={December},}
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TY - JOUR
TI - Low-Power Circuit Design Techniques for Si Bipolar Gbit/s LSIsAn Overview
T2 - IEICE TRANSACTIONS on Electronics
SP - 1511
EP - 1522
AU - Haruhiko ICHINO
PY - 1997
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E80-C
IS - 12
JA - IEICE TRANSACTIONS on Electronics
Y1 - December 1997
AB - This paper surveys low-power design techniques for Si bipolar Gbit/s LSIs. First, a total strategy for power reduction in bipolar LSIs is described. The power dissipation of Si bipolar LSIs can be minimized by reducing the supply voltage, switching and driving currents, the power of input and output circuits, and the equivalent "on" ratio. Widely spread activities from device to architecture levels are indispensable and each of the low-power techniques reduces power by a factor of about 0.5 to 0.7. The integration of these techniques is very important, and as a certain example of their effectiveness, an SOH signal processing LSI is demonstrated with a reduction factor of 1/10. Comparisons with other device technologies for low power characteristics reveal the low-power potential of bipolar LSIs in the Gbit/s region.
ER -
English
