A 3 to 5-GHz Si-bipolar quadrature modulator and demodulator are described. Both feature a wideband frequency-doubling 90-degree phase shifter that has a mechanism for self-correction of phase errors caused by an original 90-degree phase-shift network at the half frequency of the carrier. Therefore, the phase shifter produces accurate quadrature carrier signals with doubled frequency. The quadrature modulator and demodulator in 30-GHz Si bipolar technology dissipate 80 mA at a 3-V supply. Image rejection of the modulator is more than 40 dB between 3.2 to 5.2 GHz. The phase and amplitude errors of the demodulator are less than 1.5 degrees and less than 0.15 dB, respectively, between 3.5 to 5.2 GHz. Therefore, both are suitable for either direct conversion or image-rejection transceivers for 5-GHz applications.

20-Gbit/s multiplexer (MUX) and demultiplexer (DEMUX) ICs are successfully fabricated using production-level high-performance super-self-aligned silicon bipolar transistors (HSSTs) with a unity current gain cutoff frequency of 50 GHz and a maximum oscillation frequency of 65 GHz.

A very low spurious frequency doubler for wireless communication systems is proposed. The key to this technique is to change the input signal into a rectangular wave, which effectively suppresses the fundamental frequency and the odd harmonic components. The desired to undesired signal ratio (D/U) is better than 50 dBc at the desired output frequency of 1.1 GHz. The proposed doubler eliminates the need for the band-pass filters which occupy a large part of the radio frequency (RF) module. High order multipliers easily are fabricated with this method. In this paper, a quadrupler is also described.

This paper describes a 2.5-Gb/s optical receiver and transmitter chipset consisting of a preamplifier, a main amplifier, a clock and data recovery (CDR) circuit, and a laser-diode (LD) driver. Low-voltage and adjustment-free circuit techniques are introduced in order to achieve low cost and low power circuits. Circuit adjustments are eliminated by using a multi-stage automatic offset canceling technique in the main amplifier, and by using a PLL structure with a sample-and-hold technique in the CDR circuit. For power reduction, ICs are operated at a power supply voltage of -3 V. Fabricating the ICs by a 0.5-µm Si bipolar process makes it possible to achieve 2.5-Gb/s receiver and transmitter operation with a total power dissipation of 1.04 W. Especially significant is that the receiver ICs need no external devices and adjustments.

A 2-GHz monolithic Si-bipolar logarithmic/ limiting amplifier is described. It features a waveform-dependent current phase shifter that compensates for the intrinsic dependence of unit-amplifier phase shifts on input signal amplitudes and layout techniques that minimize crosstalk in Si substrate. The amplifier dissipates 250 mW at a 3-V supply, which is less than 1/4 of that of previously reported ICs. The dynamic range of a received signal strength indicator (RSSI) is 60 dB and the limited-output phase deviation is less than 7 deg. at 2 GHz. Therefore, this amplifier is quite suitable for single-conversion transceivers for broadband wireless access systems.

This paper surveys low-power design techniques for Si bipolar Gbit/s LSIs. First, a total strategy for power reduction in bipolar LSIs is described. The power dissipation of Si bipolar LSIs can be minimized by reducing the supply voltage, switching and driving currents, the power of input and output circuits, and the equivalent "on" ratio. Widely spread activities from device to architecture levels are indispensable and each of the low-power techniques reduces power by a factor of about 0.5 to 0.7. The integration of these techniques is very important, and as a certain example of their effectiveness, an SOH signal processing LSI is demonstrated with a reduction factor of 1/10. Comparisons with other device technologies for low power characteristics reveal the low-power potential of bipolar LSIs in the Gbit/s region.

A computer-aided low-power design methodology for very high-speed Si bipolar standard cell LSI is described. In order to obtain Gbit/s-speed operation, it features a pair of differential clock channels inside cells and a highly accurate static timing analysis for back annotation. A newly developed CAD-based power optimization scheme minimizes cell currents while maintaining circuit speed. A 5.6 k gate SDH signal-processing LSI operating at 1.6 Gbit/s with only 3.9 W power consumption demonstrates the effectiveness of this design technology.

A 2.7-V Si-bipolar quadrature modulator with a 90 phase shifter consisting of a frequency doubler and a master-slave flip-flop is described. The modulator operates over a wide bandwidth (0.95 to 1.88 GHz) without any tuning or adjustments. It is implemented using 20-GHz Si-bipolar technology and dissipates 97 mW at 2.7 V. An image ratio of less than -40 dBc is obtained between 1.1 and 1.8 GHz. Moreover, third-order harmonic products are less than -40 dBc and carrier leakage is less than -30 dBc.