Design and Architecture for Low-Power/High-Speed RISC Microprocessor: SuperH

Hideo MAEJIMA; Masahiro KAINAGA; Kunio UCHIYAMA

Design and Architecture for Low-Power/High-Speed RISC Microprocessor: SuperH

Hideo MAEJIMA, Masahiro KAINAGA, Kunio UCHIYAMA

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This paper describes the design and architecture for a newly developed microprocessor suitable for consumer applications, which we call SuperH. To achieve both low-power and high-speed, the SuperH architecture includes 16-bit fixed length instruction code and several power saving features. The 16-bit fixed length instruction code makes the SuperH possible to achieve excellent code efficiency for the SPECint benchmarks when compared with conventional microcontrollers and RISC's for workstations and PC's. As a result, the SuperH provides almost the same code efficiency as that of 8-bit microcontrollers, and also achieves similar performance as that of RISC's with 32-bit fixed length instruction code. The SuperH also incorporates several power reduction techniques through the control of clock frequency and clock distribution. Thus, the 16-bit code format, power saving features, and other architectural innovations make the SuperH particularly proficient for portable multi-media applications.

Publication: IEICE TRANSACTIONS on Electronics Vol.E80-C No.12 pp.1539-1545

Publication Date: 1997/12/25

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Type of Manuscript: Special Section INVITED PAPER (Special Issue on Low-Power and High-Speed LSI Technologies)

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Hideo MAEJIMA, Masahiro KAINAGA, Kunio UCHIYAMA, "Design and Architecture for Low-Power/High-Speed RISC Microprocessor: SuperH" in IEICE TRANSACTIONS on Electronics, vol. E80-C, no. 12, pp. 1539-1545, December 1997, doi: .
Abstract: This paper describes the design and architecture for a newly developed microprocessor suitable for consumer applications, which we call SuperH. To achieve both low-power and high-speed, the SuperH architecture includes 16-bit fixed length instruction code and several power saving features. The 16-bit fixed length instruction code makes the SuperH possible to achieve excellent code efficiency for the SPECint benchmarks when compared with conventional microcontrollers and RISC's for workstations and PC's. As a result, the SuperH provides almost the same code efficiency as that of 8-bit microcontrollers, and also achieves similar performance as that of RISC's with 32-bit fixed length instruction code. The SuperH also incorporates several power reduction techniques through the control of clock frequency and clock distribution. Thus, the 16-bit code format, power saving features, and other architectural innovations make the SuperH particularly proficient for portable multi-media applications.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e80-c_12_1539/_p

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@ARTICLE{e80-c_12_1539,
author={Hideo MAEJIMA, Masahiro KAINAGA, Kunio UCHIYAMA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Design and Architecture for Low-Power/High-Speed RISC Microprocessor: SuperH},
year={1997},
volume={E80-C},
number={12},
pages={1539-1545},
abstract={This paper describes the design and architecture for a newly developed microprocessor suitable for consumer applications, which we call SuperH. To achieve both low-power and high-speed, the SuperH architecture includes 16-bit fixed length instruction code and several power saving features. The 16-bit fixed length instruction code makes the SuperH possible to achieve excellent code efficiency for the SPECint benchmarks when compared with conventional microcontrollers and RISC's for workstations and PC's. As a result, the SuperH provides almost the same code efficiency as that of 8-bit microcontrollers, and also achieves similar performance as that of RISC's with 32-bit fixed length instruction code. The SuperH also incorporates several power reduction techniques through the control of clock frequency and clock distribution. Thus, the 16-bit code format, power saving features, and other architectural innovations make the SuperH particularly proficient for portable multi-media applications.},
keywords={},
doi={},
ISSN={},
month={December},}

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TY - JOUR
TI - Design and Architecture for Low-Power/High-Speed RISC Microprocessor: SuperH
T2 - IEICE TRANSACTIONS on Electronics
SP - 1539
EP - 1545
AU - Hideo MAEJIMA
AU - Masahiro KAINAGA
AU - Kunio UCHIYAMA
PY - 1997
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E80-C
IS - 12
JA - IEICE TRANSACTIONS on Electronics
Y1 - December 1997
AB - This paper describes the design and architecture for a newly developed microprocessor suitable for consumer applications, which we call SuperH. To achieve both low-power and high-speed, the SuperH architecture includes 16-bit fixed length instruction code and several power saving features. The 16-bit fixed length instruction code makes the SuperH possible to achieve excellent code efficiency for the SPECint benchmarks when compared with conventional microcontrollers and RISC's for workstations and PC's. As a result, the SuperH provides almost the same code efficiency as that of 8-bit microcontrollers, and also achieves similar performance as that of RISC's with 32-bit fixed length instruction code. The SuperH also incorporates several power reduction techniques through the control of clock frequency and clock distribution. Thus, the 16-bit code format, power saving features, and other architectural innovations make the SuperH particularly proficient for portable multi-media applications.
ER -