Temperature Characteristics of Lateral Power MOS FET Formed by Solid Phase Epitaxy

Masahito KODAMA; Tsutomu UESUGI

Temperature Characteristics of Lateral Power MOS FET Formed by Solid Phase Epitaxy

Masahito KODAMA, Tsutomu UESUGI

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We fabricated a new lateral Power MOS FET with an SOI structure formed by a solid phase epitaxy method which has a buried gate under the channel layer and a trench gate/drain. We studied the temperature dependence of the Vg-Id characteristic and Vd-Id characteristic in the temperature range of from 27 to 150. In the Vd-Id characteristic, the drain current decreases as the temperature increases in the saturation region, but the drain current increases as the temperature increases in the linear region. Zero-temperature-coefficient bias point of Vg-Id characteristic was 0. 3 V. And, the threshold voltage variation was -2. 8 mV/. In the Vd-Id characteristic, the drain current decreases as the temperature increases. The specific on-resistance was obtained in the linear region of the Vd-Id characteristic. The specific on-resistance variation was 0. 3 mWmm²/. The temperature characteristics of this device are as good as those of the conventional MOS FET.

Publication: IEICE TRANSACTIONS on Electronics Vol.E81-C No.9 pp.1505-1507

Publication Date: 1998/09/25

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Category: Semiconductor Materials and Devices

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Masahito KODAMA, Tsutomu UESUGI, "Temperature Characteristics of Lateral Power MOS FET Formed by Solid Phase Epitaxy" in IEICE TRANSACTIONS on Electronics, vol. E81-C, no. 9, pp. 1505-1507, September 1998, doi: .
Abstract: We fabricated a new lateral Power MOS FET with an SOI structure formed by a solid phase epitaxy method which has a buried gate under the channel layer and a trench gate/drain. We studied the temperature dependence of the Vg-Id characteristic and Vd-Id characteristic in the temperature range of from 27 to 150. In the Vd-Id characteristic, the drain current decreases as the temperature increases in the saturation region, but the drain current increases as the temperature increases in the linear region. Zero-temperature-coefficient bias point of Vg-Id characteristic was 0. 3 V. And, the threshold voltage variation was -2. 8 mV/. In the Vd-Id characteristic, the drain current decreases as the temperature increases. The specific on-resistance was obtained in the linear region of the Vd-Id characteristic. The specific on-resistance variation was 0. 3 mWmm²/. The temperature characteristics of this device are as good as those of the conventional MOS FET.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e81-c_9_1505/_p

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@ARTICLE{e81-c_9_1505,
author={Masahito KODAMA, Tsutomu UESUGI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Temperature Characteristics of Lateral Power MOS FET Formed by Solid Phase Epitaxy},
year={1998},
volume={E81-C},
number={9},
pages={1505-1507},
abstract={We fabricated a new lateral Power MOS FET with an SOI structure formed by a solid phase epitaxy method which has a buried gate under the channel layer and a trench gate/drain. We studied the temperature dependence of the Vg-Id characteristic and Vd-Id characteristic in the temperature range of from 27 to 150. In the Vd-Id characteristic, the drain current decreases as the temperature increases in the saturation region, but the drain current increases as the temperature increases in the linear region. Zero-temperature-coefficient bias point of Vg-Id characteristic was 0. 3 V. And, the threshold voltage variation was -2. 8 mV/. In the Vd-Id characteristic, the drain current decreases as the temperature increases. The specific on-resistance was obtained in the linear region of the Vd-Id characteristic. The specific on-resistance variation was 0. 3 mWmm²/. The temperature characteristics of this device are as good as those of the conventional MOS FET.},
keywords={},
doi={},
ISSN={},
month={September},}

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TY - JOUR
TI - Temperature Characteristics of Lateral Power MOS FET Formed by Solid Phase Epitaxy
T2 - IEICE TRANSACTIONS on Electronics
SP - 1505
EP - 1507
AU - Masahito KODAMA
AU - Tsutomu UESUGI
PY - 1998
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E81-C
IS - 9
JA - IEICE TRANSACTIONS on Electronics
Y1 - September 1998
AB - We fabricated a new lateral Power MOS FET with an SOI structure formed by a solid phase epitaxy method which has a buried gate under the channel layer and a trench gate/drain. We studied the temperature dependence of the Vg-Id characteristic and Vd-Id characteristic in the temperature range of from 27 to 150. In the Vd-Id characteristic, the drain current decreases as the temperature increases in the saturation region, but the drain current increases as the temperature increases in the linear region. Zero-temperature-coefficient bias point of Vg-Id characteristic was 0. 3 V. And, the threshold voltage variation was -2. 8 mV/. In the Vd-Id characteristic, the drain current decreases as the temperature increases. The specific on-resistance was obtained in the linear region of the Vd-Id characteristic. The specific on-resistance variation was 0. 3 mWmm²/. The temperature characteristics of this device are as good as those of the conventional MOS FET.
ER -