Current-Sensed SRAM Techniques for Megabit-Class Integration--Progress in Operating Frequency by Using Hidden Writing-Recovery Architecture--

Nobutaro SHIBATA

Summary :

A new data-I/O scheme with a hidden writing-recovery architecture has been developed for the megabit-class high operating frequency SRAMs. Read-out nodes in the memory cell are separated from bitline-connected writing nodes so as not to delay sensing initiation due to uncompleted bitline recovery. The data stored in a memory cell are read-out by sensing the differential current signal on a double-rail virtual-GND line along bitlines. Each pair of virtual-GND lines is imaginarily short-circuited by a sense amplifier, so that the read-out circuitry would have large immunity against virtual-GND-line noises. The critical noise level associated with data destruction is analyzed at various supply voltages. The virtual-GND-line-sensed memory cell with the squashed topology, the swing-suppression-type low-power writing circuitry, and the current-sense amplifier with extra negative feedback loops, --which are used in the data-I/O scheme are also mentioned. Assuming a sub array in megabit-class SRAMs, 4 K-words 6 -bits test chip was fabricated with a 0.5-µm CMOS process. The SRAM achieved 180-MHz operation at a typical 3.3-V, 25 condition. The power dissipation at the practical operating frequency of 133-MHz was 50-mW.

• Publication: IEICE TRANSACTIONS on Electronics Vol.E82-C No.11 pp.2056-2064
• Publication Date: 1999/11/25
• Type of Manuscript: PAPER
• Category: Integrated Electronics

Authors

Nobutaro SHIBATA

Keyword

SRAM,  high speed,  writing-recovery,  current sense,  virtual-GND line,  squashed memory cell