IEICE TRANSACTIONS on Electronics
Megabit-Class Size-Configurable 250-MHz SRAM Macrocells with a Squashed-Memory-Cell Architecture
Summary :
High-speed and low-power techniques are described for megabit-class size-configurable CMOS SRAM macrocells. To shorten the design turn-around-time, the methodology of abutting nine kinds of leaf cells is employed; two-level via-hole programming and the array-address decoder embedded in each control leaf cell present a divided-memory-array structure. A new squashed-memory-cell architecture using trench isolation and stacked-via-holes is proposed to reduce access times and power dissipation. To shorten the time for writing data, per-bitline architecture is proposed, in which every bitline has a personal writing driver. Also, read-out circuitry using a current-sense-type two-stage sense amplifier is designed. The effect of the non-multiplexed bitline scheme for fast read-out is shown in a simulation result. To reduce the noise from the second- to first-stage amplifier due to a feedback loop, current paths are separated so as not to cause common impedance. To confirm the techniques described in this paper, a 1-Mb SRAM test chip was fabricated with an advanced 0.35-µm CMOS/bulk process. The SRAM has demonstrated 250-MHz operation with a 2.5-V typical power supply. Also, 100-mW power dissipation was obtained at a practical operating frequency of 150-MHz.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E82-C No.1 pp.94-104
- Publication Date
- 1999/01/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- PAPER
- Category
- Integrated Electronics
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Nobutaro SHIBATA, Hiroshi INOKAWA, Keiichiro TOKUNAGA, Soichi OHTA, "Megabit-Class Size-Configurable 250-MHz SRAM Macrocells with a Squashed-Memory-Cell Architecture" in IEICE TRANSACTIONS on Electronics,
vol. E82-C, no. 1, pp. 94-104, January 1999, doi: .
Abstract: High-speed and low-power techniques are described for megabit-class size-configurable CMOS SRAM macrocells. To shorten the design turn-around-time, the methodology of abutting nine kinds of leaf cells is employed; two-level via-hole programming and the array-address decoder embedded in each control leaf cell present a divided-memory-array structure. A new squashed-memory-cell architecture using trench isolation and stacked-via-holes is proposed to reduce access times and power dissipation. To shorten the time for writing data, per-bitline architecture is proposed, in which every bitline has a personal writing driver. Also, read-out circuitry using a current-sense-type two-stage sense amplifier is designed. The effect of the non-multiplexed bitline scheme for fast read-out is shown in a simulation result. To reduce the noise from the second- to first-stage amplifier due to a feedback loop, current paths are separated so as not to cause common impedance. To confirm the techniques described in this paper, a 1-Mb SRAM test chip was fabricated with an advanced 0.35-µm CMOS/bulk process. The SRAM has demonstrated 250-MHz operation with a 2.5-V typical power supply. Also, 100-mW power dissipation was obtained at a practical operating frequency of 150-MHz.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e82-c_1_94/_p
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@ARTICLE{e82-c_1_94,
author={Nobutaro SHIBATA, Hiroshi INOKAWA, Keiichiro TOKUNAGA, Soichi OHTA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Megabit-Class Size-Configurable 250-MHz SRAM Macrocells with a Squashed-Memory-Cell Architecture},
year={1999},
volume={E82-C},
number={1},
pages={94-104},
abstract={High-speed and low-power techniques are described for megabit-class size-configurable CMOS SRAM macrocells. To shorten the design turn-around-time, the methodology of abutting nine kinds of leaf cells is employed; two-level via-hole programming and the array-address decoder embedded in each control leaf cell present a divided-memory-array structure. A new squashed-memory-cell architecture using trench isolation and stacked-via-holes is proposed to reduce access times and power dissipation. To shorten the time for writing data, per-bitline architecture is proposed, in which every bitline has a personal writing driver. Also, read-out circuitry using a current-sense-type two-stage sense amplifier is designed. The effect of the non-multiplexed bitline scheme for fast read-out is shown in a simulation result. To reduce the noise from the second- to first-stage amplifier due to a feedback loop, current paths are separated so as not to cause common impedance. To confirm the techniques described in this paper, a 1-Mb SRAM test chip was fabricated with an advanced 0.35-µm CMOS/bulk process. The SRAM has demonstrated 250-MHz operation with a 2.5-V typical power supply. Also, 100-mW power dissipation was obtained at a practical operating frequency of 150-MHz.},
keywords={},
doi={},
ISSN={},
month={January},}
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TY - JOUR
TI - Megabit-Class Size-Configurable 250-MHz SRAM Macrocells with a Squashed-Memory-Cell Architecture
T2 - IEICE TRANSACTIONS on Electronics
SP - 94
EP - 104
AU - Nobutaro SHIBATA
AU - Hiroshi INOKAWA
AU - Keiichiro TOKUNAGA
AU - Soichi OHTA
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E82-C
IS - 1
JA - IEICE TRANSACTIONS on Electronics
Y1 - January 1999
AB - High-speed and low-power techniques are described for megabit-class size-configurable CMOS SRAM macrocells. To shorten the design turn-around-time, the methodology of abutting nine kinds of leaf cells is employed; two-level via-hole programming and the array-address decoder embedded in each control leaf cell present a divided-memory-array structure. A new squashed-memory-cell architecture using trench isolation and stacked-via-holes is proposed to reduce access times and power dissipation. To shorten the time for writing data, per-bitline architecture is proposed, in which every bitline has a personal writing driver. Also, read-out circuitry using a current-sense-type two-stage sense amplifier is designed. The effect of the non-multiplexed bitline scheme for fast read-out is shown in a simulation result. To reduce the noise from the second- to first-stage amplifier due to a feedback loop, current paths are separated so as not to cause common impedance. To confirm the techniques described in this paper, a 1-Mb SRAM test chip was fabricated with an advanced 0.35-µm CMOS/bulk process. The SRAM has demonstrated 250-MHz operation with a 2.5-V typical power supply. Also, 100-mW power dissipation was obtained at a practical operating frequency of 150-MHz.
ER -
English
