Verification of Wafer Test Process Simulation in VLSI Manufacturing System and Its Application

Akihisa CHIKAMURA; Koji NAKAMAE; Hiromu FUJIOKA

Verification of Wafer Test Process Simulation in VLSI Manufacturing System and Its Application

Akihisa CHIKAMURA, Koji NAKAMAE, Hiromu FUJIOKA

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Our simulation method by using a combination of discrete event simulation and detailed parametric models of the VLSI manufacturing test system is verified by comparing simulated results with actual ones of a real wafer test facility of one-chip microcomputer in a Japanese semiconductor company. The simulated results are found to be in close agreement with the actual ones. As an application of the verified simulation method, we evaluate the economic effect of the introduction in the wafer test process of LSI testers that allows us to test multiple chips simultaneously. It is found that the optimum number of chips simultaneously tested by an LSI tester is 4 when considering both of the test cost per chip and the average test TAT.

Publication: IEICE TRANSACTIONS on Electronics Vol.E82-C No.6 pp.1013-1017

Publication Date: 1999/06/25

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Type of Manuscript: PAPER

Category: Integrated Electronics

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Akihisa CHIKAMURA, Koji NAKAMAE, Hiromu FUJIOKA, "Verification of Wafer Test Process Simulation in VLSI Manufacturing System and Its Application" in IEICE TRANSACTIONS on Electronics, vol. E82-C, no. 6, pp. 1013-1017, June 1999, doi: .
Abstract: Our simulation method by using a combination of discrete event simulation and detailed parametric models of the VLSI manufacturing test system is verified by comparing simulated results with actual ones of a real wafer test facility of one-chip microcomputer in a Japanese semiconductor company. The simulated results are found to be in close agreement with the actual ones. As an application of the verified simulation method, we evaluate the economic effect of the introduction in the wafer test process of LSI testers that allows us to test multiple chips simultaneously. It is found that the optimum number of chips simultaneously tested by an LSI tester is 4 when considering both of the test cost per chip and the average test TAT.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e82-c_6_1013/_p

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@ARTICLE{e82-c_6_1013,
author={Akihisa CHIKAMURA, Koji NAKAMAE, Hiromu FUJIOKA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Verification of Wafer Test Process Simulation in VLSI Manufacturing System and Its Application},
year={1999},
volume={E82-C},
number={6},
pages={1013-1017},
abstract={Our simulation method by using a combination of discrete event simulation and detailed parametric models of the VLSI manufacturing test system is verified by comparing simulated results with actual ones of a real wafer test facility of one-chip microcomputer in a Japanese semiconductor company. The simulated results are found to be in close agreement with the actual ones. As an application of the verified simulation method, we evaluate the economic effect of the introduction in the wafer test process of LSI testers that allows us to test multiple chips simultaneously. It is found that the optimum number of chips simultaneously tested by an LSI tester is 4 when considering both of the test cost per chip and the average test TAT.},
keywords={},
doi={},
ISSN={},
month={June},}

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TY - JOUR
TI - Verification of Wafer Test Process Simulation in VLSI Manufacturing System and Its Application
T2 - IEICE TRANSACTIONS on Electronics
SP - 1013
EP - 1017
AU - Akihisa CHIKAMURA
AU - Koji NAKAMAE
AU - Hiromu FUJIOKA
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E82-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 1999
AB - Our simulation method by using a combination of discrete event simulation and detailed parametric models of the VLSI manufacturing test system is verified by comparing simulated results with actual ones of a real wafer test facility of one-chip microcomputer in a Japanese semiconductor company. The simulated results are found to be in close agreement with the actual ones. As an application of the verified simulation method, we evaluate the economic effect of the introduction in the wafer test process of LSI testers that allows us to test multiple chips simultaneously. It is found that the optimum number of chips simultaneously tested by an LSI tester is 4 when considering both of the test cost per chip and the average test TAT.
ER -