IEICE TRANSACTIONS on Electronics
A 1 V, 10.4 mW Low Power DSP Core for Mobile Wireless Use
Summary :
An 1 V, 50 MHz, 16-bit DSP core was developed using a 0.25-µm Dual Vt library, SRAM, and Mask ROM tailored for 1 V operation. The core speed was 41% enhanced using an alternate MAC and 2-stage execution pipeline. A 1.0 V to 1.5 V voltage up converter with 59% power efficiency and a 450 ps 1 V to 2.5 V level converter were implemented. An new long wire delay estimation method enhanced the synthesis. The measured power consumption at 0.9 V was 8.7 mW, which was 40% less than the power of the normal library's at 1.3 V, when the PSI-CELP CODEC firmware was run at 40 MHz.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E83-C No.11 pp.1739-1746
- Publication Date
- 2000/11/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on Low-power LSIs and Technologies)
- Category
Authors
Shoichiro KAWASHIMA
Tetsuyoshi SHIOTA
Isao FUKUSHI
Ryuhei SASAGAWA
Wataru SHIBAMOTO
Atsushi TSUCHIYA
Teruo ISHIHARA
Keyword
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Shoichiro KAWASHIMA, Tetsuyoshi SHIOTA, Isao FUKUSHI, Ryuhei SASAGAWA, Wataru SHIBAMOTO, Atsushi TSUCHIYA, Teruo ISHIHARA, "A 1 V, 10.4 mW Low Power DSP Core for Mobile Wireless Use" in IEICE TRANSACTIONS on Electronics,
vol. E83-C, no. 11, pp. 1739-1746, November 2000, doi: .
Abstract: An 1 V, 50 MHz, 16-bit DSP core was developed using a 0.25-µm Dual Vt library, SRAM, and Mask ROM tailored for 1 V operation. The core speed was 41% enhanced using an alternate MAC and 2-stage execution pipeline. A 1.0 V to 1.5 V voltage up converter with 59% power efficiency and a 450 ps 1 V to 2.5 V level converter were implemented. An new long wire delay estimation method enhanced the synthesis. The measured power consumption at 0.9 V was 8.7 mW, which was 40% less than the power of the normal library's at 1.3 V, when the PSI-CELP CODEC firmware was run at 40 MHz.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e83-c_11_1739/_p
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@ARTICLE{e83-c_11_1739,
author={Shoichiro KAWASHIMA, Tetsuyoshi SHIOTA, Isao FUKUSHI, Ryuhei SASAGAWA, Wataru SHIBAMOTO, Atsushi TSUCHIYA, Teruo ISHIHARA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 1 V, 10.4 mW Low Power DSP Core for Mobile Wireless Use},
year={2000},
volume={E83-C},
number={11},
pages={1739-1746},
abstract={An 1 V, 50 MHz, 16-bit DSP core was developed using a 0.25-µm Dual Vt library, SRAM, and Mask ROM tailored for 1 V operation. The core speed was 41% enhanced using an alternate MAC and 2-stage execution pipeline. A 1.0 V to 1.5 V voltage up converter with 59% power efficiency and a 450 ps 1 V to 2.5 V level converter were implemented. An new long wire delay estimation method enhanced the synthesis. The measured power consumption at 0.9 V was 8.7 mW, which was 40% less than the power of the normal library's at 1.3 V, when the PSI-CELP CODEC firmware was run at 40 MHz.},
keywords={},
doi={},
ISSN={},
month={November},}
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TY - JOUR
TI - A 1 V, 10.4 mW Low Power DSP Core for Mobile Wireless Use
T2 - IEICE TRANSACTIONS on Electronics
SP - 1739
EP - 1746
AU - Shoichiro KAWASHIMA
AU - Tetsuyoshi SHIOTA
AU - Isao FUKUSHI
AU - Ryuhei SASAGAWA
AU - Wataru SHIBAMOTO
AU - Atsushi TSUCHIYA
AU - Teruo ISHIHARA
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E83-C
IS - 11
JA - IEICE TRANSACTIONS on Electronics
Y1 - November 2000
AB - An 1 V, 50 MHz, 16-bit DSP core was developed using a 0.25-µm Dual Vt library, SRAM, and Mask ROM tailored for 1 V operation. The core speed was 41% enhanced using an alternate MAC and 2-stage execution pipeline. A 1.0 V to 1.5 V voltage up converter with 59% power efficiency and a 450 ps 1 V to 2.5 V level converter were implemented. An new long wire delay estimation method enhanced the synthesis. The measured power consumption at 0.9 V was 8.7 mW, which was 40% less than the power of the normal library's at 1.3 V, when the PSI-CELP CODEC firmware was run at 40 MHz.
ER -
English
