Superconnect Technology
Summary :
Future electronic systems can not be built only with System-on-a-Chip (SoC), since many SoC issues have become evident. Relatively low yield due to the larger die size and the huge investment in developing the process to embed different kinds of technologies are some of the issues. Instead, superconnect technology is getting more important as a viable solution in building electronic systems. The superconnect connects separately built and tested chips not by the printed circuit board but rather directly to construct high-performance yet low-cost electronic systems and may use around 10 micron level design rules. System-in-a-Package and stacked chips using interposers are some realization of the superconnect. The superconnect will also be used to mitigate IR-drop problems and RC delay problems in global on-chip interconnect.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E84-C No.12 pp.1709-1716
- Publication Date
- 2001/12/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section INVITED PAPER (Special Issue on Integrated Systems with New Concepts)
- Category
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Takayasu SAKURAI, "Superconnect Technology" in IEICE TRANSACTIONS on Electronics,
vol. E84-C, no. 12, pp. 1709-1716, December 2001, doi: .
Abstract: Future electronic systems can not be built only with System-on-a-Chip (SoC), since many SoC issues have become evident. Relatively low yield due to the larger die size and the huge investment in developing the process to embed different kinds of technologies are some of the issues. Instead, superconnect technology is getting more important as a viable solution in building electronic systems. The superconnect connects separately built and tested chips not by the printed circuit board but rather directly to construct high-performance yet low-cost electronic systems and may use around 10 micron level design rules. System-in-a-Package and stacked chips using interposers are some realization of the superconnect. The superconnect will also be used to mitigate IR-drop problems and RC delay problems in global on-chip interconnect.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e84-c_12_1709/_p
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@ARTICLE{e84-c_12_1709,
author={Takayasu SAKURAI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Superconnect Technology},
year={2001},
volume={E84-C},
number={12},
pages={1709-1716},
abstract={Future electronic systems can not be built only with System-on-a-Chip (SoC), since many SoC issues have become evident. Relatively low yield due to the larger die size and the huge investment in developing the process to embed different kinds of technologies are some of the issues. Instead, superconnect technology is getting more important as a viable solution in building electronic systems. The superconnect connects separately built and tested chips not by the printed circuit board but rather directly to construct high-performance yet low-cost electronic systems and may use around 10 micron level design rules. System-in-a-Package and stacked chips using interposers are some realization of the superconnect. The superconnect will also be used to mitigate IR-drop problems and RC delay problems in global on-chip interconnect.},
keywords={},
doi={},
ISSN={},
month={December},}
Copy
TY - JOUR
TI - Superconnect Technology
T2 - IEICE TRANSACTIONS on Electronics
SP - 1709
EP - 1716
AU - Takayasu SAKURAI
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E84-C
IS - 12
JA - IEICE TRANSACTIONS on Electronics
Y1 - December 2001
AB - Future electronic systems can not be built only with System-on-a-Chip (SoC), since many SoC issues have become evident. Relatively low yield due to the larger die size and the huge investment in developing the process to embed different kinds of technologies are some of the issues. Instead, superconnect technology is getting more important as a viable solution in building electronic systems. The superconnect connects separately built and tested chips not by the printed circuit board but rather directly to construct high-performance yet low-cost electronic systems and may use around 10 micron level design rules. System-in-a-Package and stacked chips using interposers are some realization of the superconnect. The superconnect will also be used to mitigate IR-drop problems and RC delay problems in global on-chip interconnect.
ER -
English
