Low-Power VLSI Architecture for a New Block-Matching Motion Estimation Algorithm Using Dual-Bit-Resolution Images
Summary :
This paper describes an improved multiresolution telescopic search algorithm (MRTlcSA) for block-matching motion estimation. The algorithm uses images with full and reduced bit resolution, and uses motion-track and adaptive-search-window strategies. Simulation results show that the proposed algorithm has low computational complexity and achieves good image quality. We have developed a systolic-architecture-based search engine that has split data paths. In the case of low bit-resolution, the throughput is increased by enhancing the operating parallelism. The new motion estimator works at a low clock frequency and a low supply voltage, and therefore has low power consumption.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E84-C No.3 pp.399-409
- Publication Date
- 2001/03/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- PAPER
- Category
- Integrated Electronics
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Wujian ZHANG, Runde ZHOU, Tsunehachi ISHITANI, Ryota KASAI, Toshio KONDO, "Low-Power VLSI Architecture for a New Block-Matching Motion Estimation Algorithm Using Dual-Bit-Resolution Images" in IEICE TRANSACTIONS on Electronics,
vol. E84-C, no. 3, pp. 399-409, March 2001, doi: .
Abstract: This paper describes an improved multiresolution telescopic search algorithm (MRTlcSA) for block-matching motion estimation. The algorithm uses images with full and reduced bit resolution, and uses motion-track and adaptive-search-window strategies. Simulation results show that the proposed algorithm has low computational complexity and achieves good image quality. We have developed a systolic-architecture-based search engine that has split data paths. In the case of low bit-resolution, the throughput is increased by enhancing the operating parallelism. The new motion estimator works at a low clock frequency and a low supply voltage, and therefore has low power consumption.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e84-c_3_399/_p
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@ARTICLE{e84-c_3_399,
author={Wujian ZHANG, Runde ZHOU, Tsunehachi ISHITANI, Ryota KASAI, Toshio KONDO, },
journal={IEICE TRANSACTIONS on Electronics},
title={Low-Power VLSI Architecture for a New Block-Matching Motion Estimation Algorithm Using Dual-Bit-Resolution Images},
year={2001},
volume={E84-C},
number={3},
pages={399-409},
abstract={This paper describes an improved multiresolution telescopic search algorithm (MRTlcSA) for block-matching motion estimation. The algorithm uses images with full and reduced bit resolution, and uses motion-track and adaptive-search-window strategies. Simulation results show that the proposed algorithm has low computational complexity and achieves good image quality. We have developed a systolic-architecture-based search engine that has split data paths. In the case of low bit-resolution, the throughput is increased by enhancing the operating parallelism. The new motion estimator works at a low clock frequency and a low supply voltage, and therefore has low power consumption.},
keywords={},
doi={},
ISSN={},
month={March},}
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TY - JOUR
TI - Low-Power VLSI Architecture for a New Block-Matching Motion Estimation Algorithm Using Dual-Bit-Resolution Images
T2 - IEICE TRANSACTIONS on Electronics
SP - 399
EP - 409
AU - Wujian ZHANG
AU - Runde ZHOU
AU - Tsunehachi ISHITANI
AU - Ryota KASAI
AU - Toshio KONDO
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E84-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 2001
AB - This paper describes an improved multiresolution telescopic search algorithm (MRTlcSA) for block-matching motion estimation. The algorithm uses images with full and reduced bit resolution, and uses motion-track and adaptive-search-window strategies. Simulation results show that the proposed algorithm has low computational complexity and achieves good image quality. We have developed a systolic-architecture-based search engine that has split data paths. In the case of low bit-resolution, the throughput is increased by enhancing the operating parallelism. The new motion estimator works at a low clock frequency and a low supply voltage, and therefore has low power consumption.
ER -
English
