Thanks to rapid progress in computer technology and VLSI technology, we are approaching the stage where ordinary PCs will be able to handle real-time video signals as easily as they handle text data. First, features and applications of the video compression standard MPEG2 are surveyed as a typical video processing. It is clarified that real-time capability becomes more important as applications of MPEG2 widely spread. The trends of video coding in LSIs are summarized. And it is shown that the most advanced encoder/decoder LSI has an improved price-performance ratio that allows it to be adopted in consumer equipment. Finally, future directions of parallel architecture in video processing are surveyed in terms of special-purpose and general-purpose processing. The special approach has always taken the lead in video processing using sophisticated hardware-oriented parallel architectures. The general-purpose architecture method has gradually evolved in accordance with a software-oriented architecture. Both approaches will continue to evolve into a new stage by selecting possible parallel architectures such as multimedia instruction sets and process-level parallelism, and applying them in compound use. The so-called super processor architecture will emerge in the near future and it will be an ideal method that can manage rapid increase in requirements of capability and applicability in video processing.

This paper describes an improved multiresolution telescopic search algorithm (MRTlcSA) for block-matching motion estimation. The algorithm uses images with full and reduced bit resolution, and uses motion-track and adaptive-search-window strategies. Simulation results show that the proposed algorithm has low computational complexity and achieves good image quality. We have developed a systolic-architecture-based search engine that has split data paths. In the case of low bit-resolution, the throughput is increased by enhancing the operating parallelism. The new motion estimator works at a low clock frequency and a low supply voltage, and therefore has low power consumption.

There are two approaches to implementing the international standard video coding algorithms such as H.261 and MPEG: a programmable DSP approach and a building block approach. The advantages and disadvantages of each are discussed here in detail, and the video coding algorithms and required throughput are also summarized. For more complex standard such as MPEG-, VLSI architecuture became more sophisticated. The DSP approach incorporates special processing engines and the building block approach integrates general-purpose microprocessors. Both approaches are capable of MPEG- NTSC coding in a single chip. Reduction of power consumption is a key issue for video LSIs. Architectures and circuits that reduce the supply voltage while maintaining throughput are summarized. A 0.25-µm, 3-GOPS, 0.5-W, SIMD-VSP for portable MPEG- systems could be made by using architecture-driven voltage scaling as well as feature-size scaling and SOI devices.

The ring-like systolic array architecture described in this paper, based on a conventional one-dimensional systolic array architecture, was created through operator rescheduling based on the symmetry of data flow. This eliminated high-latency delay due to the stuffing of the array pipeline in the conventional architecture. The new architecture requires a memory bandwidth no greater than the conventional architecture does, but increases throughput and processor utilization while reducing power consumption.