Binary code representation successfully reducing device count for radix-2 Signed-Digit arithmetic has been proposed and an adder using this binary code has been designed. Delay time of addition is estimated at 5.5 ns regardless of digit length using 1.2 µm CMOS technology. The occupied area is almost the same compared with CLA.

Three custom LSIs for EB60, a direct wafer exposure electron beam system, have been developed using 0.8 µm BiCMOS and SST bipolar technologies. The three LSIs are i) a shot cycle control LSI for controlling each exposure cycle time, ii) a linear matrix computation LSI for coordinate modification of the exposure pattern data, and iii) a position calculation LSI for determining the precise position of the wafer. These LSIs allow the deflection corrector block of the revised EB60 to be realized on a single board. A new adaptive pipeline control technique which optimizes each shot period according to the exposure data is implemented in the shot-cycle control LSI. The position calculation LSI implements a new, highly effective 2-level pipeline exposure technique, the levels refer to major-field-deflection and minor-field-deflection. The linear-matrix computation LSI is designed not only for the EB60 but also for a wide variety of parallel digital processing applications.

Most communication cables are laid underground. In order to make construction and maintenance works easier, systems to detect buried objects have already been developed using the electromagnetic pulse radar technique. However, existing detection systems are not really practical due to their rather limited processing speed. To achieve sufficient processing speed, two dedicated custom FFT LSI's are designed and realized with 0.8 µm-CMOS technology. The two chips have an equivalent processing capacity of 200 MOPS. An efficietn hardware algorithm for address generation and 2 word parallel processing are introduced. In addition, an enhanced system organization is developed together with an improved pattern recognition scheme and aperture synthesis hardware. The new processor executes a FFT/parameter extraction operation in 4 seconds and aperture synthesis in 1 second. This speed meets the design target, and a real time detection system for underground objects becomes possible.

A new blind restoration method applying Real-coded genetic algorithm (RcGA) will be proposed, and this method will be proven valid for the blurred image restoration with unidentified degradation in the experiments. In this restoration method, the degraded and blurred image is going to get restricted to the images possible to be expressed in the point spread function (PSF), then the restoration filter for this degraded image, which is also the 2-dimentional inverse filter, will be searched among several points applying RcGA. The method will enable to seek efficiently among vast solution space consists of numeral coefficient filters. And perceiving the essential features of the spectrum in the frequency space, an evaluation function will be proposed. Also, it will be proposed to apply the Rolling-ball transform succeeding an appropriate Gaussian degrade function against the dual degraded image with blur convoluting impulse noise. By above stated features of this restoration method, it will enable to restore the degraded image closer to the original within a practical processing time. Computer simulations verify this method for image restoration problem when the factors causing image distortions are not identified.

Some dedicated floating-point hardware arithmetic modules designed as processing elements for butterfly operations are described. They consist of Input Data Converters (IDC), Output Data Converters (ODC), and a 2's complementary 24-bit (16E8) floating-point Butterfly Execution Unit (BEU). The BEU executes the four multiplication and six additions/subtractions required for a complex butterfly operation in each 25-ns execution cycle by implementing four multipliers and four 3-input adders/subtracters. The arithmetic modules are fabricated using 0.8-µm CMOS technology. An overview of the hardware unit is presented with special attention given to the BEU for parallel pipelined processing. In addition, module design methodologies for hardware implementation and some sophisticated high-speed execution techniques for floating-point multiplication and addition are discussed.

Thanks to rapid progress in computer technology and VLSI technology, we are approaching the stage where ordinary PCs will be able to handle real-time video signals as easily as they handle text data. First, features and applications of the video compression standard MPEG2 are surveyed as a typical video processing. It is clarified that real-time capability becomes more important as applications of MPEG2 widely spread. The trends of video coding in LSIs are summarized. And it is shown that the most advanced encoder/decoder LSI has an improved price-performance ratio that allows it to be adopted in consumer equipment. Finally, future directions of parallel architecture in video processing are surveyed in terms of special-purpose and general-purpose processing. The special approach has always taken the lead in video processing using sophisticated hardware-oriented parallel architectures. The general-purpose architecture method has gradually evolved in accordance with a software-oriented architecture. Both approaches will continue to evolve into a new stage by selecting possible parallel architectures such as multimedia instruction sets and process-level parallelism, and applying them in compound use. The so-called super processor architecture will emerge in the near future and it will be an ideal method that can manage rapid increase in requirements of capability and applicability in video processing.

This paper presents a method for LSI implementation of a long-tap acoustic echo canceller algorithm using the residue number system (RNS) and the mixed-radix number system (MRS). It also presents a quantitative comparison of echo canceller architectures, one using the RNS and the other using the binary number system (BNS). In the RNS, addition, subtraction, and multiplication are executed quickly but scaling, overflow detection, and division are difficult. For this reason, no echo canceller using the RNS has been implemented. We therefore try to design an echo canceller architecture using the RNS and the NLMS algorithm. It is shown that the echo canceller algorithm can be effectively implemented using the RNS by introducing the MRS. The quantitative comparison of echo canceller architectures shows that a long-tap acoustic echo canceller can be implemented more effectively in terms of chip size and power dissipation by the architecture using the RNS.

We propose a single-chip 400-MFLOPS 2-D FFT processor VLSI architecture. This processor integrates 380,000 transistors in an area of 11.5811.58 mm2 using 0.8 µm CMOS technology with a typical machine cycle time of 25 ns, and executes 2n2n point 2-D FFT in real time, e.g., 256256 point FFT is executed in 14 ms. This excellent performance in terms of both speed and dynamic range makes the real-time processing practical for video as well as speech processing.