The search functionality is under construction.

Author Search Result

[Author] Tsutomu HOSAKA(2hit)

1-2hit
  • A High-Speed Special Purpose Processor for Underground Object Detection

    Hiroshi MIYANAGA  Hironori YAMAUCHI  Yuji NAGASHIMA  Tsutomu HOSAKA  

     
    PAPER-Application Specific Processors

      Vol:
    E75-C No:10
      Page(s):
    1250-1258

    Most communication cables are laid underground. In order to make construction and maintenance works easier, systems to detect buried objects have already been developed using the electromagnetic pulse radar technique. However, existing detection systems are not really practical due to their rather limited processing speed. To achieve sufficient processing speed, two dedicated custom FFT LSI's are designed and realized with 0.8 µm-CMOS technology. The two chips have an equivalent processing capacity of 200 MOPS. An efficietn hardware algorithm for address generation and 2 word parallel processing are introduced. In addition, an enhanced system organization is developed together with an improved pattern recognition scheme and aperture synthesis hardware. The new processor executes a FFT/parameter extraction operation in 4 seconds and aperture synthesis in 1 second. This speed meets the design target, and a real time detection system for underground objects becomes possible.

  • Real-Time Feed-Forward Control LSIs for a Direct Wafer Exposure Electron Beam System

    Hironori YAMAUCHI  Tetsuo MOROSAWA  Takashi WATANABE  Atsushi IWATA  Tsutomu HOSAKA  

     
    PAPER-Integrated Electronics

      Vol:
    E76-C No:1
      Page(s):
    124-135

    Three custom LSIs for EB60, a direct wafer exposure electron beam system, have been developed using 0.8 µm BiCMOS and SST bipolar technologies. The three LSIs are i) a shot cycle control LSI for controlling each exposure cycle time, ii) a linear matrix computation LSI for coordinate modification of the exposure pattern data, and iii) a position calculation LSI for determining the precise position of the wafer. These LSIs allow the deflection corrector block of the revised EB60 to be realized on a single board. A new adaptive pipeline control technique which optimizes each shot period according to the exposure data is implemented in the shot-cycle control LSI. The position calculation LSI implements a new, highly effective 2-level pipeline exposure technique, the levels refer to major-field-deflection and minor-field-deflection. The linear-matrix computation LSI is designed not only for the EB60 but also for a wide variety of parallel digital processing applications.