IEICE TRANSACTIONS on Electronics
Physical Design Methodology for On-Chip 64-Mb DRAM MPEG-2 Encoding with a Multimedia Processor
Summary :
An on-chip, 64-Mb, embedded, DRAM MPEG-2 encoder LSI with a multimedia processor has been developed. To implement this large-scale and high-speed LSI, we have developed the hierarchical skew control of multi-clocks, with timing verification, in which cross-talk noise is considered, and simple measures taken against the IR drop in the power lines through decoupling capacitors. As a result, the target performance of 263 MHz at 1.5 V has been successfully attained and verified, the cross-talk noise has been considered, and, in addition, it has become possible to restrain the IR drop to 166 mV in the 162 MHz operation block.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E85-C No.2 pp.368-374
- Publication Date
- 2002/02/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on High-Performance and Low-Power Microprocessors)
- Category
- Product Designs
Authors
Hidehiro TAKATA
Rei AKIYAMA
Tadao YAMANAKA
Haruyuki OHKUMA
Yasue SUETSUGU
Toshihiro KANAOKA
Satoshi KUMAKI
Kazuya ISHIHARA
Atsuo HANAMI
Tetsuya MATSUMURA
Tetsuya WATANABE
Yoshihide AJIOKA
Yoshio MATSUDA
Syuhei IWADE
Keyword
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Hidehiro TAKATA, Rei AKIYAMA, Tadao YAMANAKA, Haruyuki OHKUMA, Yasue SUETSUGU, Toshihiro KANAOKA, Satoshi KUMAKI, Kazuya ISHIHARA, Atsuo HANAMI, Tetsuya MATSUMURA, Tetsuya WATANABE, Yoshihide AJIOKA, Yoshio MATSUDA, Syuhei IWADE, "Physical Design Methodology for On-Chip 64-Mb DRAM MPEG-2 Encoding with a Multimedia Processor" in IEICE TRANSACTIONS on Electronics,
vol. E85-C, no. 2, pp. 368-374, February 2002, doi: .
Abstract: An on-chip, 64-Mb, embedded, DRAM MPEG-2 encoder LSI with a multimedia processor has been developed. To implement this large-scale and high-speed LSI, we have developed the hierarchical skew control of multi-clocks, with timing verification, in which cross-talk noise is considered, and simple measures taken against the IR drop in the power lines through decoupling capacitors. As a result, the target performance of 263 MHz at 1.5 V has been successfully attained and verified, the cross-talk noise has been considered, and, in addition, it has become possible to restrain the IR drop to 166 mV in the 162 MHz operation block.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e85-c_2_368/_p
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@ARTICLE{e85-c_2_368,
author={Hidehiro TAKATA, Rei AKIYAMA, Tadao YAMANAKA, Haruyuki OHKUMA, Yasue SUETSUGU, Toshihiro KANAOKA, Satoshi KUMAKI, Kazuya ISHIHARA, Atsuo HANAMI, Tetsuya MATSUMURA, Tetsuya WATANABE, Yoshihide AJIOKA, Yoshio MATSUDA, Syuhei IWADE, },
journal={IEICE TRANSACTIONS on Electronics},
title={Physical Design Methodology for On-Chip 64-Mb DRAM MPEG-2 Encoding with a Multimedia Processor},
year={2002},
volume={E85-C},
number={2},
pages={368-374},
abstract={An on-chip, 64-Mb, embedded, DRAM MPEG-2 encoder LSI with a multimedia processor has been developed. To implement this large-scale and high-speed LSI, we have developed the hierarchical skew control of multi-clocks, with timing verification, in which cross-talk noise is considered, and simple measures taken against the IR drop in the power lines through decoupling capacitors. As a result, the target performance of 263 MHz at 1.5 V has been successfully attained and verified, the cross-talk noise has been considered, and, in addition, it has become possible to restrain the IR drop to 166 mV in the 162 MHz operation block.},
keywords={},
doi={},
ISSN={},
month={February},}
Copy
TY - JOUR
TI - Physical Design Methodology for On-Chip 64-Mb DRAM MPEG-2 Encoding with a Multimedia Processor
T2 - IEICE TRANSACTIONS on Electronics
SP - 368
EP - 374
AU - Hidehiro TAKATA
AU - Rei AKIYAMA
AU - Tadao YAMANAKA
AU - Haruyuki OHKUMA
AU - Yasue SUETSUGU
AU - Toshihiro KANAOKA
AU - Satoshi KUMAKI
AU - Kazuya ISHIHARA
AU - Atsuo HANAMI
AU - Tetsuya MATSUMURA
AU - Tetsuya WATANABE
AU - Yoshihide AJIOKA
AU - Yoshio MATSUDA
AU - Syuhei IWADE
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E85-C
IS - 2
JA - IEICE TRANSACTIONS on Electronics
Y1 - February 2002
AB - An on-chip, 64-Mb, embedded, DRAM MPEG-2 encoder LSI with a multimedia processor has been developed. To implement this large-scale and high-speed LSI, we have developed the hierarchical skew control of multi-clocks, with timing verification, in which cross-talk noise is considered, and simple measures taken against the IR drop in the power lines through decoupling capacitors. As a result, the target performance of 263 MHz at 1.5 V has been successfully attained and verified, the cross-talk noise has been considered, and, in addition, it has become possible to restrain the IR drop to 166 mV in the 162 MHz operation block.
ER -
English
