IEICE TRANSACTIONS on Electronics
High-Speed and Low-Power Techniques of Hardware and Software for Digital Signal Processors
Summary :
High-speed and low-power DSPs have been developed for versatile hand set applications. The DSP contains a 16-bit fixed point DSP core with multiple buses, highly tuned instruction sets and a low-power architecture, featuring CPU power with 404.5 µ W/MHz, chip power with 2.08 mW/MHz at peak and 200 µA stand-by current and 160 MHz/160 MIPS performance by a single DSP core, and also operates at 0.68 V within the temperature range from -40
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E86-C No.4 pp.589-596
- Publication Date
- 2003/04/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on High-Performance, Low-Power System LSIs and Related Technologies)
- Category
- Circuit Design
Authors
Hiroshi TAKAHASHI
Rimon IKENO
Yutaka TOYONOH
Akihiro TAKEGAMA
Yasumasa IKEZAKI
Tohru URASAKI
Hitoshi SATOH
Masayasu ITOIGAWA
Yoshinari MATSUMOTO
Keyword
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Hiroshi TAKAHASHI, Rimon IKENO, Yutaka TOYONOH, Akihiro TAKEGAMA, Yasumasa IKEZAKI, Tohru URASAKI, Hitoshi SATOH, Masayasu ITOIGAWA, Yoshinari MATSUMOTO, "High-Speed and Low-Power Techniques of Hardware and Software for Digital Signal Processors" in IEICE TRANSACTIONS on Electronics,
vol. E86-C, no. 4, pp. 589-596, April 2003, doi: .
Abstract: High-speed and low-power DSPs have been developed for versatile hand set applications. The DSP contains a 16-bit fixed point DSP core with multiple buses, highly tuned instruction sets and a low-power architecture, featuring CPU power with 404.5 µ W/MHz, chip power with 2.08 mW/MHz at peak and 200 µA stand-by current and 160 MHz/160 MIPS performance by a single DSP core, and also operates at 0.68 V within the temperature range from -40
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e86-c_4_589/_p
Copy
@ARTICLE{e86-c_4_589,
author={Hiroshi TAKAHASHI, Rimon IKENO, Yutaka TOYONOH, Akihiro TAKEGAMA, Yasumasa IKEZAKI, Tohru URASAKI, Hitoshi SATOH, Masayasu ITOIGAWA, Yoshinari MATSUMOTO, },
journal={IEICE TRANSACTIONS on Electronics},
title={High-Speed and Low-Power Techniques of Hardware and Software for Digital Signal Processors},
year={2003},
volume={E86-C},
number={4},
pages={589-596},
abstract={High-speed and low-power DSPs have been developed for versatile hand set applications. The DSP contains a 16-bit fixed point DSP core with multiple buses, highly tuned instruction sets and a low-power architecture, featuring CPU power with 404.5 µ W/MHz, chip power with 2.08 mW/MHz at peak and 200 µA stand-by current and 160 MHz/160 MIPS performance by a single DSP core, and also operates at 0.68 V within the temperature range from -40
keywords={},
doi={},
ISSN={},
month={April},}
Copy
TY - JOUR
TI - High-Speed and Low-Power Techniques of Hardware and Software for Digital Signal Processors
T2 - IEICE TRANSACTIONS on Electronics
SP - 589
EP - 596
AU - Hiroshi TAKAHASHI
AU - Rimon IKENO
AU - Yutaka TOYONOH
AU - Akihiro TAKEGAMA
AU - Yasumasa IKEZAKI
AU - Tohru URASAKI
AU - Hitoshi SATOH
AU - Masayasu ITOIGAWA
AU - Yoshinari MATSUMOTO
PY - 2003
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E86-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2003
AB - High-speed and low-power DSPs have been developed for versatile hand set applications. The DSP contains a 16-bit fixed point DSP core with multiple buses, highly tuned instruction sets and a low-power architecture, featuring CPU power with 404.5 µ W/MHz, chip power with 2.08 mW/MHz at peak and 200 µA stand-by current and 160 MHz/160 MIPS performance by a single DSP core, and also operates at 0.68 V within the temperature range from -40
ER -
English
