IEICE TRANSACTIONS on Electronics
Signal Integrity Design and Analysis for a 400 MHz RISC Microcontroller
Summary :
A high-speed 32-bit RISC microcontroller has been developed. In order to realize high-speed operation with minimum hardware resource, we have developed new design and analysis methods such as a clock distribution, a bus-line layout, and an IR drop analysis. As a result, high-speed operation of 400 MHz has been achieved with power dissipation of 0.96 W at 1.8 V.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E86-C No.4 pp.635-642
- Publication Date
- 2003/04/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on High-Performance, Low-Power System LSIs and Related Technologies)
- Category
- Design Methods and Implementation
Authors
Akira YAMADA
Yasuhiro NUNOMURA
Hiroaki SUZUKI
Hisakazu SATO
Niichi ITOH
Tetsuya KAGEMOTO
Hironobu ITO
Takashi KURAFUJI
Nobuharu YOSHIOKA
Jingo NAKANISHI
Hiromi NOTANI
Rei AKIYAMA
Atsushi IWABU
Tadao YAMANAKA
Hidehiro TAKATA
Takeshi SHIBAGAKI
Takahiko ARAKAWA
Hiroshi MAKINO
Osamu TOMISAWA
Shuhei IWADE
Keyword
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Akira YAMADA, Yasuhiro NUNOMURA, Hiroaki SUZUKI, Hisakazu SATO, Niichi ITOH, Tetsuya KAGEMOTO, Hironobu ITO, Takashi KURAFUJI, Nobuharu YOSHIOKA, Jingo NAKANISHI, Hiromi NOTANI, Rei AKIYAMA, Atsushi IWABU, Tadao YAMANAKA, Hidehiro TAKATA, Takeshi SHIBAGAKI, Takahiko ARAKAWA, Hiroshi MAKINO, Osamu TOMISAWA, Shuhei IWADE, "Signal Integrity Design and Analysis for a 400 MHz RISC Microcontroller" in IEICE TRANSACTIONS on Electronics,
vol. E86-C, no. 4, pp. 635-642, April 2003, doi: .
Abstract: A high-speed 32-bit RISC microcontroller has been developed. In order to realize high-speed operation with minimum hardware resource, we have developed new design and analysis methods such as a clock distribution, a bus-line layout, and an IR drop analysis. As a result, high-speed operation of 400 MHz has been achieved with power dissipation of 0.96 W at 1.8 V.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e86-c_4_635/_p
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@ARTICLE{e86-c_4_635,
author={Akira YAMADA, Yasuhiro NUNOMURA, Hiroaki SUZUKI, Hisakazu SATO, Niichi ITOH, Tetsuya KAGEMOTO, Hironobu ITO, Takashi KURAFUJI, Nobuharu YOSHIOKA, Jingo NAKANISHI, Hiromi NOTANI, Rei AKIYAMA, Atsushi IWABU, Tadao YAMANAKA, Hidehiro TAKATA, Takeshi SHIBAGAKI, Takahiko ARAKAWA, Hiroshi MAKINO, Osamu TOMISAWA, Shuhei IWADE, },
journal={IEICE TRANSACTIONS on Electronics},
title={Signal Integrity Design and Analysis for a 400 MHz RISC Microcontroller},
year={2003},
volume={E86-C},
number={4},
pages={635-642},
abstract={A high-speed 32-bit RISC microcontroller has been developed. In order to realize high-speed operation with minimum hardware resource, we have developed new design and analysis methods such as a clock distribution, a bus-line layout, and an IR drop analysis. As a result, high-speed operation of 400 MHz has been achieved with power dissipation of 0.96 W at 1.8 V.},
keywords={},
doi={},
ISSN={},
month={April},}
Copy
TY - JOUR
TI - Signal Integrity Design and Analysis for a 400 MHz RISC Microcontroller
T2 - IEICE TRANSACTIONS on Electronics
SP - 635
EP - 642
AU - Akira YAMADA
AU - Yasuhiro NUNOMURA
AU - Hiroaki SUZUKI
AU - Hisakazu SATO
AU - Niichi ITOH
AU - Tetsuya KAGEMOTO
AU - Hironobu ITO
AU - Takashi KURAFUJI
AU - Nobuharu YOSHIOKA
AU - Jingo NAKANISHI
AU - Hiromi NOTANI
AU - Rei AKIYAMA
AU - Atsushi IWABU
AU - Tadao YAMANAKA
AU - Hidehiro TAKATA
AU - Takeshi SHIBAGAKI
AU - Takahiko ARAKAWA
AU - Hiroshi MAKINO
AU - Osamu TOMISAWA
AU - Shuhei IWADE
PY - 2003
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E86-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2003
AB - A high-speed 32-bit RISC microcontroller has been developed. In order to realize high-speed operation with minimum hardware resource, we have developed new design and analysis methods such as a clock distribution, a bus-line layout, and an IR drop analysis. As a result, high-speed operation of 400 MHz has been achieved with power dissipation of 0.96 W at 1.8 V.
ER -
English
