IEICE TRANSACTIONS on Electronics
The Design of a 2.7 V, 200 MS/s, and 14-Bit CMOS D/A Converter with 63 dB of SFDR Characteristics for the 90 MHz Output Signal
Summary :
This paper describes the design of a 2.7 V operational, 200 MS/s, 14-bit CMOS D/A converter (DAC). The DAC consists of 63 current cells in matrix form for an upper 6-bit sub-DAC, and 8 current cells and R-2R ladder resistors for a lower 8-bit sub-DAC. A source degeneration resistor, for which a transistor in the triode operational region is used, is connected to the source of a MOS current source transistor in a current cell in order to reduce the influence of threshold voltage (Vth) variation and to satisfy the differential nonlinearity error specification as a 14-bit DAC. In conventional high-speed and high-resolution DACs that have the same design specifications described here, spurious-free dynamic range (SFDR) characteristics commonly deteriorate drastically as the frequency of the reconstructed waveform increases. The causes of this deterioration were carefully examined in the present study, finding that the deterioration is caused in part by the input-data-dependent time-constant change at the output terminal. Unexpected current flow in parasitic capacitors associated with current sources causes the change in the output current depending on the input data, resulting in time-constant change. In order to solve this problem, we propose a new output circuit to fix the voltage at the node where the outputs of the current sources are combined. SPICE circuit simulation demonstrates that 63 dB of SFDR characteristics for the 90 MHz reconstructed waveform at the output can be realizable when the supply voltage is 2.7 V, the clock rate is 200 MS/s, and the power dissipation is estimated to be 300 mW.
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- IEICE TRANSACTIONS on Electronics Vol.E86-C No.6 pp.1077-1084
- Publication Date
- 2003/06/01
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- Special Section PAPER (Special Issue on Devices and Circuits for Next Generation Multi-Media Communication Systems)
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Hiroki SAKURAI, Yasuhiro SUGIMOTO, "The Design of a 2.7 V, 200 MS/s, and 14-Bit CMOS D/A Converter with 63 dB of SFDR Characteristics for the 90 MHz Output Signal" in IEICE TRANSACTIONS on Electronics,
vol. E86-C, no. 6, pp. 1077-1084, June 2003, doi: .
Abstract: This paper describes the design of a 2.7 V operational, 200 MS/s, 14-bit CMOS D/A converter (DAC). The DAC consists of 63 current cells in matrix form for an upper 6-bit sub-DAC, and 8 current cells and R-2R ladder resistors for a lower 8-bit sub-DAC. A source degeneration resistor, for which a transistor in the triode operational region is used, is connected to the source of a MOS current source transistor in a current cell in order to reduce the influence of threshold voltage (Vth) variation and to satisfy the differential nonlinearity error specification as a 14-bit DAC. In conventional high-speed and high-resolution DACs that have the same design specifications described here, spurious-free dynamic range (SFDR) characteristics commonly deteriorate drastically as the frequency of the reconstructed waveform increases. The causes of this deterioration were carefully examined in the present study, finding that the deterioration is caused in part by the input-data-dependent time-constant change at the output terminal. Unexpected current flow in parasitic capacitors associated with current sources causes the change in the output current depending on the input data, resulting in time-constant change. In order to solve this problem, we propose a new output circuit to fix the voltage at the node where the outputs of the current sources are combined. SPICE circuit simulation demonstrates that 63 dB of SFDR characteristics for the 90 MHz reconstructed waveform at the output can be realizable when the supply voltage is 2.7 V, the clock rate is 200 MS/s, and the power dissipation is estimated to be 300 mW.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e86-c_6_1077/_p
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@ARTICLE{e86-c_6_1077,
author={Hiroki SAKURAI, Yasuhiro SUGIMOTO, },
journal={IEICE TRANSACTIONS on Electronics},
title={The Design of a 2.7 V, 200 MS/s, and 14-Bit CMOS D/A Converter with 63 dB of SFDR Characteristics for the 90 MHz Output Signal},
year={2003},
volume={E86-C},
number={6},
pages={1077-1084},
abstract={This paper describes the design of a 2.7 V operational, 200 MS/s, 14-bit CMOS D/A converter (DAC). The DAC consists of 63 current cells in matrix form for an upper 6-bit sub-DAC, and 8 current cells and R-2R ladder resistors for a lower 8-bit sub-DAC. A source degeneration resistor, for which a transistor in the triode operational region is used, is connected to the source of a MOS current source transistor in a current cell in order to reduce the influence of threshold voltage (Vth) variation and to satisfy the differential nonlinearity error specification as a 14-bit DAC. In conventional high-speed and high-resolution DACs that have the same design specifications described here, spurious-free dynamic range (SFDR) characteristics commonly deteriorate drastically as the frequency of the reconstructed waveform increases. The causes of this deterioration were carefully examined in the present study, finding that the deterioration is caused in part by the input-data-dependent time-constant change at the output terminal. Unexpected current flow in parasitic capacitors associated with current sources causes the change in the output current depending on the input data, resulting in time-constant change. In order to solve this problem, we propose a new output circuit to fix the voltage at the node where the outputs of the current sources are combined. SPICE circuit simulation demonstrates that 63 dB of SFDR characteristics for the 90 MHz reconstructed waveform at the output can be realizable when the supply voltage is 2.7 V, the clock rate is 200 MS/s, and the power dissipation is estimated to be 300 mW.},
keywords={},
doi={},
ISSN={},
month={June},}
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TY - JOUR
TI - The Design of a 2.7 V, 200 MS/s, and 14-Bit CMOS D/A Converter with 63 dB of SFDR Characteristics for the 90 MHz Output Signal
T2 - IEICE TRANSACTIONS on Electronics
SP - 1077
EP - 1084
AU - Hiroki SAKURAI
AU - Yasuhiro SUGIMOTO
PY - 2003
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E86-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2003
AB - This paper describes the design of a 2.7 V operational, 200 MS/s, 14-bit CMOS D/A converter (DAC). The DAC consists of 63 current cells in matrix form for an upper 6-bit sub-DAC, and 8 current cells and R-2R ladder resistors for a lower 8-bit sub-DAC. A source degeneration resistor, for which a transistor in the triode operational region is used, is connected to the source of a MOS current source transistor in a current cell in order to reduce the influence of threshold voltage (Vth) variation and to satisfy the differential nonlinearity error specification as a 14-bit DAC. In conventional high-speed and high-resolution DACs that have the same design specifications described here, spurious-free dynamic range (SFDR) characteristics commonly deteriorate drastically as the frequency of the reconstructed waveform increases. The causes of this deterioration were carefully examined in the present study, finding that the deterioration is caused in part by the input-data-dependent time-constant change at the output terminal. Unexpected current flow in parasitic capacitors associated with current sources causes the change in the output current depending on the input data, resulting in time-constant change. In order to solve this problem, we propose a new output circuit to fix the voltage at the node where the outputs of the current sources are combined. SPICE circuit simulation demonstrates that 63 dB of SFDR characteristics for the 90 MHz reconstructed waveform at the output can be realizable when the supply voltage is 2.7 V, the clock rate is 200 MS/s, and the power dissipation is estimated to be 300 mW.
ER -
English
