IEICE TRANSACTIONS on Electronics
A Systematic Approach for Low Phase Noise CMOS VCO Design
Summary :
The fully integrated LC voltage controlled oscillator by 0.35 µm CMOS technology is demonstrated. It has 2 GHz oscillation frequency, 23.58 mW power consumption under 3 V biased and 9.1% frequency tuning. The layout optimization method of inductor to increase quality factor and also to reduce phase noise is used. A general method is proposed which is capable of making an effective prediction of F, device excess noise number, and acquiring the phase noise of oscillators accurately. From this proposed method, the low phase noise by calculation is attained. The phase noise of measured value which shows good match with calculating data is about -115.5 dBc/Hz at off set frequency 600 kHz.
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- IEICE TRANSACTIONS on Electronics Vol.E86-C No.8 pp.1427-1432
- Publication Date
- 2003/08/01
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- Special Section PAPER (Special Issue on Microwave and Millimeter Wave Technology)
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Yao-Huang KAO, Meng-Ting HSU, Min-Chieh HSU, Pi-An WU, "A Systematic Approach for Low Phase Noise CMOS VCO Design" in IEICE TRANSACTIONS on Electronics,
vol. E86-C, no. 8, pp. 1427-1432, August 2003, doi: .
Abstract: The fully integrated LC voltage controlled oscillator by 0.35 µm CMOS technology is demonstrated. It has 2 GHz oscillation frequency, 23.58 mW power consumption under 3 V biased and 9.1% frequency tuning. The layout optimization method of inductor to increase quality factor and also to reduce phase noise is used. A general method is proposed which is capable of making an effective prediction of F, device excess noise number, and acquiring the phase noise of oscillators accurately. From this proposed method, the low phase noise by calculation is attained. The phase noise of measured value which shows good match with calculating data is about -115.5 dBc/Hz at off set frequency 600 kHz.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e86-c_8_1427/_p
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@ARTICLE{e86-c_8_1427,
author={Yao-Huang KAO, Meng-Ting HSU, Min-Chieh HSU, Pi-An WU, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Systematic Approach for Low Phase Noise CMOS VCO Design},
year={2003},
volume={E86-C},
number={8},
pages={1427-1432},
abstract={The fully integrated LC voltage controlled oscillator by 0.35 µm CMOS technology is demonstrated. It has 2 GHz oscillation frequency, 23.58 mW power consumption under 3 V biased and 9.1% frequency tuning. The layout optimization method of inductor to increase quality factor and also to reduce phase noise is used. A general method is proposed which is capable of making an effective prediction of F, device excess noise number, and acquiring the phase noise of oscillators accurately. From this proposed method, the low phase noise by calculation is attained. The phase noise of measured value which shows good match with calculating data is about -115.5 dBc/Hz at off set frequency 600 kHz.},
keywords={},
doi={},
ISSN={},
month={August},}
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TY - JOUR
TI - A Systematic Approach for Low Phase Noise CMOS VCO Design
T2 - IEICE TRANSACTIONS on Electronics
SP - 1427
EP - 1432
AU - Yao-Huang KAO
AU - Meng-Ting HSU
AU - Min-Chieh HSU
AU - Pi-An WU
PY - 2003
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E86-C
IS - 8
JA - IEICE TRANSACTIONS on Electronics
Y1 - August 2003
AB - The fully integrated LC voltage controlled oscillator by 0.35 µm CMOS technology is demonstrated. It has 2 GHz oscillation frequency, 23.58 mW power consumption under 3 V biased and 9.1% frequency tuning. The layout optimization method of inductor to increase quality factor and also to reduce phase noise is used. A general method is proposed which is capable of making an effective prediction of F, device excess noise number, and acquiring the phase noise of oscillators accurately. From this proposed method, the low phase noise by calculation is attained. The phase noise of measured value which shows good match with calculating data is about -115.5 dBc/Hz at off set frequency 600 kHz.
ER -
English
