IEICE TRANSACTIONS on Electronics
Open Access
Rapid Single-Flux-Quantum Truncated Multiplier Based on Bit-Level Processing
-
Full Text Views
30
- Cite this
- Free PDF (934.3KB)
Summary :
A rapid single-flux-quantum (RSFQ) truncated multiplier based on bit-level processing is proposed. In the multiplier, two operands are transformed to two serialized patterns of bits (pulses), and the multiplication is carried out by processing those bits. The result is obtained by counting bits. By calculating in bit-level, the proposed multiplier can be implemented in small area. The gate level design of the multiplier is shown. The layout of the 4-bit multiplier was also designed.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E102-C No.7 pp.607-611
- Publication Date
- 2019/07/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.2018ECS6014
- Type of Manuscript
- BRIEF PAPER
- Category
- Superconducting Electronics
Authors
Nobutaka KITO
Chukyo University
Ryota ODAKA
Chukyo University
Kazuyoshi TAKAGI
Kyoto University
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Nobutaka KITO, Ryota ODAKA, Kazuyoshi TAKAGI, "Rapid Single-Flux-Quantum Truncated Multiplier Based on Bit-Level Processing" in IEICE TRANSACTIONS on Electronics,
vol. E102-C, no. 7, pp. 607-611, July 2019, doi: 10.1587/transele.2018ECS6014.
Abstract: A rapid single-flux-quantum (RSFQ) truncated multiplier based on bit-level processing is proposed. In the multiplier, two operands are transformed to two serialized patterns of bits (pulses), and the multiplication is carried out by processing those bits. The result is obtained by counting bits. By calculating in bit-level, the proposed multiplier can be implemented in small area. The gate level design of the multiplier is shown. The layout of the 4-bit multiplier was also designed.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.2018ECS6014/_p
Copy
@ARTICLE{e102-c_7_607,
author={Nobutaka KITO, Ryota ODAKA, Kazuyoshi TAKAGI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Rapid Single-Flux-Quantum Truncated Multiplier Based on Bit-Level Processing},
year={2019},
volume={E102-C},
number={7},
pages={607-611},
abstract={A rapid single-flux-quantum (RSFQ) truncated multiplier based on bit-level processing is proposed. In the multiplier, two operands are transformed to two serialized patterns of bits (pulses), and the multiplication is carried out by processing those bits. The result is obtained by counting bits. By calculating in bit-level, the proposed multiplier can be implemented in small area. The gate level design of the multiplier is shown. The layout of the 4-bit multiplier was also designed.},
keywords={},
doi={10.1587/transele.2018ECS6014},
ISSN={1745-1353},
month={July},}
Copy
TY - JOUR
TI - Rapid Single-Flux-Quantum Truncated Multiplier Based on Bit-Level Processing
T2 - IEICE TRANSACTIONS on Electronics
SP - 607
EP - 611
AU - Nobutaka KITO
AU - Ryota ODAKA
AU - Kazuyoshi TAKAGI
PY - 2019
DO - 10.1587/transele.2018ECS6014
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E102-C
IS - 7
JA - IEICE TRANSACTIONS on Electronics
Y1 - July 2019
AB - A rapid single-flux-quantum (RSFQ) truncated multiplier based on bit-level processing is proposed. In the multiplier, two operands are transformed to two serialized patterns of bits (pulses), and the multiplication is carried out by processing those bits. The result is obtained by counting bits. By calculating in bit-level, the proposed multiplier can be implemented in small area. The gate level design of the multiplier is shown. The layout of the 4-bit multiplier was also designed.
ER -
English
