This paper describes transmission line couplers for non-contact connecters. Their characteristics are formulated in closed forms and design methodologies are presented. As their applications, three different types of transmission line couplers, two-fold transmission line coupler, single-ended to differential conversion transmission line coupler, and rotatable transmission line coupler are reviewed.

Ring voltage-controlled-oscillators (VCOs) are increasingly being used to design ΔΣ ADCs. They have the merits of simple, highly digital and low-voltage tolerant, making them attractive alternatives for the classic scaling-unfriendly operational-amplifier-based methodology. This paper aims to provide a summary on the advancement of VCO-based ΔΣ ADCs. The scope of this paper includes the basics and motivations behind the VCO-based ADCs, followed by a survey covering a wide range of architectures and circuit techniques in both continuous-time (CT) and discrete-time (DT) implementation, and will discuss the key insights behind the contributions and drawbacks of these architectures.

This paper presents a type-I digital ring-based PLL with wide loop bandwidth to lower the ring oscillator's noise contribution. The loop delay due to the D flip-flops at filter's output is compensated in order to lower the noise peak and stably achieve wide loop bandwidth. The input-referred jitter is lowered by using a successive-approximated-register analog-to-digital converter (SAR-ADC)-based sampling phase detector (SPD). A stacked reference buffer is introduced to reduce the transient short-circuit current for low power and low reference spur. The locking issue due to the steady-state phase error in a type-I PLL and the limited range of the phase detector is addressed using a TDC-assisted loop. The loop stability and phase noise are analyzed, suggesting a trade-off for the minimum jitter. The solutions in detail are described. The prototype PLL fabricated in 65 nm CMOS demonstrates 2.0 ps RMS jitter, 3.1 mW power consumption, and 0.067 mm² area, with 50 MHz reference frequency and 2.0 GHz output frequency.

This paper presents a low-power small-area-overhead physical random number generator utilizing SAR ADC embedded in sensor SoCs. An unpredictable random bit sequence is produced by an existing comparator in typical SAR ADCs, which results in little area overhead. Unlike the other comparator-based physical random number generator, this proposed technique does not require an offset calibration scheme since SAR binary search algorithm automatically converges the two input voltages of the comparator to balance the differential circuit pair. Although the randomness slightly depends on an quantization error due to sharing AD conversion scheme, the input signal distribution enhances the quality of random number bit sequence which can use for various security countermeasures such as masking techniques. Fabricated in 180nm CMOS, 1Mb/s random bit generator achieves high efficiency of 0.72pJ/bit with only 400μm² area overhead, which occupies less than 0.5% of SAR ADC, while remaining 10-bit AD conversion function.

This paper discusses non-ideal issues in a fully passive noise shaping successive approximation register analog-to-digital converter. The fully passive noise shaping techniques are realized by switches and capacitors without operational amplifiers to be scalable and power efficient. However, some non-ideal issues, such as parasitic capacitance, comparator noise, thermal noise, will affect the performance of the noise shaping and then degrade the final achievable resolution. This paper analyzes the effects of the main non-ideal issues and provides the design reference for fully passive noise shaping techniques. The analysis is based on 2^nd order fully passive noise shaping SAR ADC with an 8-bit architecture and an OSR of 4.

In this paper, a high-frequency resolution Digital Frequency Discriminator (DFD) IC using a Time to Digital Converter (TDC) and an edge counter for Instantaneous Frequency Measurement (IFM) is proposed. In the proposed DFD, the TDC measures the time of the maximum periods of divided RF short pulse signals, and the edge counter counts the maximum number of periods of the signal. By measuring the multiple periods with the TDC and the edge counter, the proposed DFD improves the frequency resolution compared with that of the measuring one period because it is proportional to reciprocal of the measurement time of TDC. The DFD was fabricated using 0.18-um SiGe-BiCMOS. Frequency accuracy below 0.39MHz and frequency precision below 1.58 MHz-RMS were achieved during 50 ns detection time in 0.3 GHz to 5.5 GHz band with the temperature range from -40 to 85 degrees.

An integrated ambient light sensor (ALS) system in low-temperature polycrystalline silicon (LTPS) thin-film-transistor liquid-crystal-displays (TFT-LCDs) is proposed and prototyped in this study. It is designed as a 4-bit (16-step-grayscale) ALS and includes a noise subtraction circuit, a comparator as an analog-to-digital converter (ADC), 4-bit counters, and a parallel-to-serial converter. LTPS lateral p-i-n diodes with a long i-region are employed as photodetectors in the system. An LSI source driver is mounted on the LCD panel with a sensor control block which provides programmable clocks and reference voltages to the ALS circuit on the glass substrate for sensitivity tuning. The reliability tests were conducted for 300 hours with 30000 lux illumination at 70 °C and at -20 °C. The observed deviations of the ALS values for dark, 1000 lux, and 10000 lux were within ±1.

Body bias generators are useful circuits that can reduce variability and power dissipation in LSI circuits. However, the amplifier implemented into the body bias generator is difficult to design because of its complexity. To overcome the difficulty, this paper proposes a clearer cell-based design method of the amplifier than the existing cell-based design methods. The proposed method is based on a simple analytical model, which enables to easily design the amplifiers under various operating conditions. First, we introduce a small signal equivalent circuit of two-stage amplifiers by which we approximate a three-stage amplifier, and introduce a method for determining its design parameters based on the analytical model. Second, we propose a method of tuning parameters such as cell-based phase compensation elements and drive-strength of the output stage. Finally, based on the test chip measurement, we show the advantage of the body bias generator we designed in a cell-based flow over existing designs.

This paper discusses the impact of stacking on-chip inductor on power/ground network. Stacking inductor on other circuit components can reduce the circuit area drastically, however, the impact on signal and power integrity is not clear. We investigate the impact by a field-solver, a circuit simulator and real chip measurement. We evaluate three types of power/ground network and various multi-layered inductors. Experimental results show that dense power/ground structures reduce noise although the coupling capacitance becomes larger than that of sparse structures. Measurement in a 65-nm CMOS shows a woven structure makes the noise voltage half compared to a sparse structure.

An efficient resistive random access memory (ReRAM) structure is developed for accelerating convolutional neural network (CNN) powered by the in-memory computation. A novel ReRAM cell circuit is designed with two-directional (2-D) accessibility. The entire memory system is organized as a 2-D array, in which specific memory cells can be identically accessed by both of column- and row-locality. For the in-memory computations of CNNs, only relevant cells in an identical sub-array are accessed by 2-D read-out operations, which is hardly implemented by conventional ReRAM cells. In this manner, the redundant access (column or row) of the conventional ReRAM structures is prevented to eliminated the unnecessary data movement when CNNs are processed in-memory. From the simulation results, the energy and bandwidth efficiency of the proposed memory structure are 1.4x and 5x of a state-of-the-art ReRAM architecture, respectively.

This work presents an FSK inductive-coupling transceiver using a load-modulated transmitter and LC-oscillator-based receiver for energy-budget-unbalanced applications. By introducing the time-domain load modulated transmitter for FSK instead of the conventional current-driven scheme, energy reduction of the transmitter side is possible. For verifying the proposed scheme, a test chip was fabricated in 65nm CMOS, and two chips were stacked for verifying the inter-chip communication. The measurement results show 0.64fJ/bit transmitter power consumption while its input voltage is 60mV, and the communication distance is 150μm. The footprint of the transmitter is 0.0016mm².

This work presents the lowest power consumption sub-mm² supply-modulated OOK transmitter for self-powering a continuous glucose monitoring (CGM) contact lens. By combining the transmitter with a glucose fuel cell that functions as both the power source and a sensing transducer, a self-powered CGM contact lens was developed. The 385×385μm² test chip implemented in 65-nm standard CMOS technology operates at 270pW with a supply voltage of 0.165V. Self-powered operation of the transmitter using a 2×2mm² solid-state glucose fuel cell was thus demonstrated.

This paper proposes a pulse-tail-feedback VCO, in which the tail transistor is driven using pulse-shaped voltage signals with rail-to-rail swing. The proposed pulse-tail-feedback (PTFB) VCO relies on reducing the current conduction period of the tail transistor and operating the tail transistors in triode region for reducing the flicker and thermal noise from the active elements. Mathematical analysis and circuit level simulations of the phase noise mechanism in the proposed PTFB-VCO is also presented in this paper for validating the effectiveness of the proposed technique. A prototype LC-VCO with the proposed PTFB technique is fabricated in a standard 180nm CMOS. Laboratory measurement shows a power consumption of 1.35mW from a 1.2V supply at 4.6GHz. The proposed PTFB-VCO achieves a flicker corner of 700Hz, which enables the VCO to maintain a fairly constant figure-of-merit (FoM) of -195dB within a wide offset frequency range of 1kHz-10MHz.

A rapid single-flux-quantum (RSFQ) truncated multiplier based on bit-level processing is proposed. In the multiplier, two operands are transformed to two serialized patterns of bits (pulses), and the multiplication is carried out by processing those bits. The result is obtained by counting bits. By calculating in bit-level, the proposed multiplier can be implemented in small area. The gate level design of the multiplier is shown. The layout of the 4-bit multiplier was also designed.