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Crosstalk Analysis and Countermeasures of High-Bandwidth 3D-Stacked Memory Using Multi-Hop Inductive Coupling Interface
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This paper describes an in-depth analysis of crosstalk in a high-bandwidth 3D-stacked memory using a multi-hop inductive coupling interface and proposes two countermeasures. This work analyzes the crosstalk among seven stacked chips using a 3D electromagnetic (EM) simulator. The detailed analysis reveals two main crosstalk sources: concentric coils and adjacent coils. To suppress these crosstalks, this paper proposes two corresponding countermeasures: shorted coils and 8-shaped coils. The combination of these coils improves area efficiency by a factor of 4 in simulation. The proposed methods enable an area-efficient inductive coupling interface for high-bandwidth stacked memory.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E106-C No.7 pp.391-394
- Publication Date
- 2023/07/01
- Publicized
- 2022/09/30
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.2022CDS0001
- Type of Manuscript
- BRIEF PAPER
- Category
Authors
Kota SHIBA
The University of Tokyo
Atsutake KOSUGE
The University of Tokyo
Mototsugu HAMADA
The University of Tokyo
Tadahiro KURODA
The University of Tokyo
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Kota SHIBA, Atsutake KOSUGE, Mototsugu HAMADA, Tadahiro KURODA, "Crosstalk Analysis and Countermeasures of High-Bandwidth 3D-Stacked Memory Using Multi-Hop Inductive Coupling Interface" in IEICE TRANSACTIONS on Electronics,
vol. E106-C, no. 7, pp. 391-394, July 2023, doi: 10.1587/transele.2022CDS0001.
Abstract: This paper describes an in-depth analysis of crosstalk in a high-bandwidth 3D-stacked memory using a multi-hop inductive coupling interface and proposes two countermeasures. This work analyzes the crosstalk among seven stacked chips using a 3D electromagnetic (EM) simulator. The detailed analysis reveals two main crosstalk sources: concentric coils and adjacent coils. To suppress these crosstalks, this paper proposes two corresponding countermeasures: shorted coils and 8-shaped coils. The combination of these coils improves area efficiency by a factor of 4 in simulation. The proposed methods enable an area-efficient inductive coupling interface for high-bandwidth stacked memory.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.2022CDS0001/_p
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@ARTICLE{e106-c_7_391,
author={Kota SHIBA, Atsutake KOSUGE, Mototsugu HAMADA, Tadahiro KURODA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Crosstalk Analysis and Countermeasures of High-Bandwidth 3D-Stacked Memory Using Multi-Hop Inductive Coupling Interface},
year={2023},
volume={E106-C},
number={7},
pages={391-394},
abstract={This paper describes an in-depth analysis of crosstalk in a high-bandwidth 3D-stacked memory using a multi-hop inductive coupling interface and proposes two countermeasures. This work analyzes the crosstalk among seven stacked chips using a 3D electromagnetic (EM) simulator. The detailed analysis reveals two main crosstalk sources: concentric coils and adjacent coils. To suppress these crosstalks, this paper proposes two corresponding countermeasures: shorted coils and 8-shaped coils. The combination of these coils improves area efficiency by a factor of 4 in simulation. The proposed methods enable an area-efficient inductive coupling interface for high-bandwidth stacked memory.},
keywords={},
doi={10.1587/transele.2022CDS0001},
ISSN={1745-1353},
month={July},}
Copy
TY - JOUR
TI - Crosstalk Analysis and Countermeasures of High-Bandwidth 3D-Stacked Memory Using Multi-Hop Inductive Coupling Interface
T2 - IEICE TRANSACTIONS on Electronics
SP - 391
EP - 394
AU - Kota SHIBA
AU - Atsutake KOSUGE
AU - Mototsugu HAMADA
AU - Tadahiro KURODA
PY - 2023
DO - 10.1587/transele.2022CDS0001
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E106-C
IS - 7
JA - IEICE TRANSACTIONS on Electronics
Y1 - July 2023
AB - This paper describes an in-depth analysis of crosstalk in a high-bandwidth 3D-stacked memory using a multi-hop inductive coupling interface and proposes two countermeasures. This work analyzes the crosstalk among seven stacked chips using a 3D electromagnetic (EM) simulator. The detailed analysis reveals two main crosstalk sources: concentric coils and adjacent coils. To suppress these crosstalks, this paper proposes two corresponding countermeasures: shorted coils and 8-shaped coils. The combination of these coils improves area efficiency by a factor of 4 in simulation. The proposed methods enable an area-efficient inductive coupling interface for high-bandwidth stacked memory.
ER -
English
