IEICE TRANSACTIONS on Electronics
Quick-Start Pulse Width Controlled PLL with Frequency and Phase Presetting
Summary :
This paper demonstrates a quick start method for Pulse-Width Controlled PLL (PWPLL). Our PLL converts the internal state into digital signals and stores them into a memory before getting into a sleep mode. The wakeup sequence reads the memory and presets the internal state so that our PLL can start the operation with close to the previously locked condition. Since the internal state includes not only the frequency control code but also the phase information, our quick start PLL locks in several clock cycles. A prototype chip fabricated in 0.18µm standard CMOS shows 50ns settling time (4 reference clock cycles), 18.5mW power consumption under 1.8V nominal supply voltage with 105µm×870µm silicon area.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E101-C No.4 pp.218-223
- Publication Date
- 2018/04/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E101.C.218
- Type of Manuscript
- Special Section PAPER (Special Section on Solid-State Circuit Design — Architecture, Circuit, Device and Design Methodology)
- Category
Authors
Toru NAKURA
The University of Tokyo
Tsukasa KAGAYA
The University of Tokyo
Tetsuya IIZUKA
The University of Tokyo
Kunihiro ASADA
The University of Tokyo
Keyword
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Toru NAKURA, Tsukasa KAGAYA, Tetsuya IIZUKA, Kunihiro ASADA, "Quick-Start Pulse Width Controlled PLL with Frequency and Phase Presetting" in IEICE TRANSACTIONS on Electronics,
vol. E101-C, no. 4, pp. 218-223, April 2018, doi: 10.1587/transele.E101.C.218.
Abstract: This paper demonstrates a quick start method for Pulse-Width Controlled PLL (PWPLL). Our PLL converts the internal state into digital signals and stores them into a memory before getting into a sleep mode. The wakeup sequence reads the memory and presets the internal state so that our PLL can start the operation with close to the previously locked condition. Since the internal state includes not only the frequency control code but also the phase information, our quick start PLL locks in several clock cycles. A prototype chip fabricated in 0.18µm standard CMOS shows 50ns settling time (4 reference clock cycles), 18.5mW power consumption under 1.8V nominal supply voltage with 105µm×870µm silicon area.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E101.C.218/_p
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@ARTICLE{e101-c_4_218,
author={Toru NAKURA, Tsukasa KAGAYA, Tetsuya IIZUKA, Kunihiro ASADA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Quick-Start Pulse Width Controlled PLL with Frequency and Phase Presetting},
year={2018},
volume={E101-C},
number={4},
pages={218-223},
abstract={This paper demonstrates a quick start method for Pulse-Width Controlled PLL (PWPLL). Our PLL converts the internal state into digital signals and stores them into a memory before getting into a sleep mode. The wakeup sequence reads the memory and presets the internal state so that our PLL can start the operation with close to the previously locked condition. Since the internal state includes not only the frequency control code but also the phase information, our quick start PLL locks in several clock cycles. A prototype chip fabricated in 0.18µm standard CMOS shows 50ns settling time (4 reference clock cycles), 18.5mW power consumption under 1.8V nominal supply voltage with 105µm×870µm silicon area.},
keywords={},
doi={10.1587/transele.E101.C.218},
ISSN={1745-1353},
month={April},}
Copy
TY - JOUR
TI - Quick-Start Pulse Width Controlled PLL with Frequency and Phase Presetting
T2 - IEICE TRANSACTIONS on Electronics
SP - 218
EP - 223
AU - Toru NAKURA
AU - Tsukasa KAGAYA
AU - Tetsuya IIZUKA
AU - Kunihiro ASADA
PY - 2018
DO - 10.1587/transele.E101.C.218
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E101-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2018
AB - This paper demonstrates a quick start method for Pulse-Width Controlled PLL (PWPLL). Our PLL converts the internal state into digital signals and stores them into a memory before getting into a sleep mode. The wakeup sequence reads the memory and presets the internal state so that our PLL can start the operation with close to the previously locked condition. Since the internal state includes not only the frequency control code but also the phase information, our quick start PLL locks in several clock cycles. A prototype chip fabricated in 0.18µm standard CMOS shows 50ns settling time (4 reference clock cycles), 18.5mW power consumption under 1.8V nominal supply voltage with 105µm×870µm silicon area.
ER -
English
