Design of SCR-Based ESD Protection Device for Power Clamp Using Deep-Submicron CMOS Technology
Summary :
The novel SCR-based (silicon controlled rectifier) device for ESD power clamp is presented in this paper. The proposed device has a high holding voltage and a high triggering current characteristic. These characteristics enable latch-up immune normal operation as well as superior full chip ESD protection. The device has a small area in requirement robustness in comparison to ggNMOS (gate grounded NMOS). The proposed ESD protection device is designed in 0.25 µm and 0.5 µm CMOS Technology. In the experimental result, the proposed ESD clamp has a double trigger characteristic, a high holding voltage of 4 V and a high trigger current of above 350 mA. The robustness has measured to HBM 8 kV (HBM: Human Body Model) and MM 400 V (MM: Machine Model). The proposed device has a high level It2 of 52 mA/ µm approximately.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E92-C No.9 pp.1188-1193
- Publication Date
- 2009/09/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E92.C.1188
- Type of Manuscript
- PAPER
- Category
- Electronic Circuits
Authors
Keyword
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Yongseo KOO, "Design of SCR-Based ESD Protection Device for Power Clamp Using Deep-Submicron CMOS Technology" in IEICE TRANSACTIONS on Electronics,
vol. E92-C, no. 9, pp. 1188-1193, September 2009, doi: 10.1587/transele.E92.C.1188.
Abstract: The novel SCR-based (silicon controlled rectifier) device for ESD power clamp is presented in this paper. The proposed device has a high holding voltage and a high triggering current characteristic. These characteristics enable latch-up immune normal operation as well as superior full chip ESD protection. The device has a small area in requirement robustness in comparison to ggNMOS (gate grounded NMOS). The proposed ESD protection device is designed in 0.25 µm and 0.5 µm CMOS Technology. In the experimental result, the proposed ESD clamp has a double trigger characteristic, a high holding voltage of 4 V and a high trigger current of above 350 mA. The robustness has measured to HBM 8 kV (HBM: Human Body Model) and MM 400 V (MM: Machine Model). The proposed device has a high level It2 of 52 mA/ µm approximately.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E92.C.1188/_p
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@ARTICLE{e92-c_9_1188,
author={Yongseo KOO, },
journal={IEICE TRANSACTIONS on Electronics},
title={Design of SCR-Based ESD Protection Device for Power Clamp Using Deep-Submicron CMOS Technology},
year={2009},
volume={E92-C},
number={9},
pages={1188-1193},
abstract={The novel SCR-based (silicon controlled rectifier) device for ESD power clamp is presented in this paper. The proposed device has a high holding voltage and a high triggering current characteristic. These characteristics enable latch-up immune normal operation as well as superior full chip ESD protection. The device has a small area in requirement robustness in comparison to ggNMOS (gate grounded NMOS). The proposed ESD protection device is designed in 0.25 µm and 0.5 µm CMOS Technology. In the experimental result, the proposed ESD clamp has a double trigger characteristic, a high holding voltage of 4 V and a high trigger current of above 350 mA. The robustness has measured to HBM 8 kV (HBM: Human Body Model) and MM 400 V (MM: Machine Model). The proposed device has a high level It2 of 52 mA/ µm approximately.},
keywords={},
doi={10.1587/transele.E92.C.1188},
ISSN={1745-1353},
month={September},}
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TY - JOUR
TI - Design of SCR-Based ESD Protection Device for Power Clamp Using Deep-Submicron CMOS Technology
T2 - IEICE TRANSACTIONS on Electronics
SP - 1188
EP - 1193
AU - Yongseo KOO
PY - 2009
DO - 10.1587/transele.E92.C.1188
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E92-C
IS - 9
JA - IEICE TRANSACTIONS on Electronics
Y1 - September 2009
AB - The novel SCR-based (silicon controlled rectifier) device for ESD power clamp is presented in this paper. The proposed device has a high holding voltage and a high triggering current characteristic. These characteristics enable latch-up immune normal operation as well as superior full chip ESD protection. The device has a small area in requirement robustness in comparison to ggNMOS (gate grounded NMOS). The proposed ESD protection device is designed in 0.25 µm and 0.5 µm CMOS Technology. In the experimental result, the proposed ESD clamp has a double trigger characteristic, a high holding voltage of 4 V and a high trigger current of above 350 mA. The robustness has measured to HBM 8 kV (HBM: Human Body Model) and MM 400 V (MM: Machine Model). The proposed device has a high level It2 of 52 mA/ µm approximately.
ER -
English
