A Low-Power Reduced Kick-Back Comparator with Improved Calibration for High-Speed Flash ADCs
Summary :
A novel low-power kick-back reduced comparator for use in high-speed flash analog-to-digital converters (ADC) is presented. The proposed comparator combines cascode transistors to reduce the kick-back noise with a built-in threshold voltage to remove the static power consumption of a reference. Without degrading other figures, the kick-back noise is reduced by a factor 8, compared to a previous design without cascode transistors. An improved calibration structure is also proposed to improve linearity when used in an ADC. Simulated in a standard CMOS technology the comparator consumes 106.5 µW at 1.8 V power supply and 1 GHz clock frequency.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E92-C No.10 pp.1328-1330
- Publication Date
- 2009/10/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E92.C.1328
- Type of Manuscript
- LETTER
- Category
- Electronic Components
Authors
Keyword
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Guy TORFS, Zhisheng LI, Johan BAUWELINCK, Xin YIN, Jan VANDEWEGE, Geert Van Der PLAS, "A Low-Power Reduced Kick-Back Comparator with Improved Calibration for High-Speed Flash ADCs" in IEICE TRANSACTIONS on Electronics,
vol. E92-C, no. 10, pp. 1328-1330, October 2009, doi: 10.1587/transele.E92.C.1328.
Abstract: A novel low-power kick-back reduced comparator for use in high-speed flash analog-to-digital converters (ADC) is presented. The proposed comparator combines cascode transistors to reduce the kick-back noise with a built-in threshold voltage to remove the static power consumption of a reference. Without degrading other figures, the kick-back noise is reduced by a factor 8, compared to a previous design without cascode transistors. An improved calibration structure is also proposed to improve linearity when used in an ADC. Simulated in a standard CMOS technology the comparator consumes 106.5 µW at 1.8 V power supply and 1 GHz clock frequency.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E92.C.1328/_p
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@ARTICLE{e92-c_10_1328,
author={Guy TORFS, Zhisheng LI, Johan BAUWELINCK, Xin YIN, Jan VANDEWEGE, Geert Van Der PLAS, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Low-Power Reduced Kick-Back Comparator with Improved Calibration for High-Speed Flash ADCs},
year={2009},
volume={E92-C},
number={10},
pages={1328-1330},
abstract={A novel low-power kick-back reduced comparator for use in high-speed flash analog-to-digital converters (ADC) is presented. The proposed comparator combines cascode transistors to reduce the kick-back noise with a built-in threshold voltage to remove the static power consumption of a reference. Without degrading other figures, the kick-back noise is reduced by a factor 8, compared to a previous design without cascode transistors. An improved calibration structure is also proposed to improve linearity when used in an ADC. Simulated in a standard CMOS technology the comparator consumes 106.5 µW at 1.8 V power supply and 1 GHz clock frequency.},
keywords={},
doi={10.1587/transele.E92.C.1328},
ISSN={1745-1353},
month={October},}
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TY - JOUR
TI - A Low-Power Reduced Kick-Back Comparator with Improved Calibration for High-Speed Flash ADCs
T2 - IEICE TRANSACTIONS on Electronics
SP - 1328
EP - 1330
AU - Guy TORFS
AU - Zhisheng LI
AU - Johan BAUWELINCK
AU - Xin YIN
AU - Jan VANDEWEGE
AU - Geert Van Der PLAS
PY - 2009
DO - 10.1587/transele.E92.C.1328
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E92-C
IS - 10
JA - IEICE TRANSACTIONS on Electronics
Y1 - October 2009
AB - A novel low-power kick-back reduced comparator for use in high-speed flash analog-to-digital converters (ADC) is presented. The proposed comparator combines cascode transistors to reduce the kick-back noise with a built-in threshold voltage to remove the static power consumption of a reference. Without degrading other figures, the kick-back noise is reduced by a factor 8, compared to a previous design without cascode transistors. An improved calibration structure is also proposed to improve linearity when used in an ADC. Simulated in a standard CMOS technology the comparator consumes 106.5 µW at 1.8 V power supply and 1 GHz clock frequency.
ER -
English
