The ROM Design with Half Grouping Compression Method for Chip Area and Power Consumption Reduction

Ki-Sang JUNG; Kang-Jik KIM; Young-Eun KIM; Jin-Gyun CHUNG; Ki-Hyun PYUN; Jong-Yeol LEE; Hang-Geun JEONG; Seong-Ik CHO

doi:10.1587/transele.E92.C.352

The ROM Design with Half Grouping Compression Method for Chip Area and Power Consumption Reduction

Ki-Sang JUNG, Kang-Jik KIM, Young-Eun KIM, Jin-Gyun CHUNG, Ki-Hyun PYUN, Jong-Yeol LEE, Hang-Geun JEONG, Seong-Ik CHO

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In memory design, the issue is smaller size and low power. Most power used in the ROM is consumed in line capacitance such as address lines, word lines, bit lines, and decoder. This paper presents ROM design of a novel HG (Half Grouping) compression method so as to reduce the parasitic capacitance of bit lines and the area of the row decoder for power consumption and chip area reduction. ROM design result of 512 point FFT block shows that the proposed method reduces 40.6% area, 42.12% power, and 37.82% transistor number respectively in comparison with the conventional method. The designed ROM with proposed method is implemented in a 0.35 µm CMOS process. It consumes 5.8 mW at 100 MHz with a single 3.3 V power supply.

Publication: IEICE TRANSACTIONS on Electronics Vol.E92-C No.3 pp.352-355

Publication Date: 2009/03/01

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Online ISSN: 1745-1353

DOI: 10.1587/transele.E92.C.352

Type of Manuscript: PAPER

Category: Integrated Electronics

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Ki-Sang JUNG, Kang-Jik KIM, Young-Eun KIM, Jin-Gyun CHUNG, Ki-Hyun PYUN, Jong-Yeol LEE, Hang-Geun JEONG, Seong-Ik CHO, "The ROM Design with Half Grouping Compression Method for Chip Area and Power Consumption Reduction" in IEICE TRANSACTIONS on Electronics, vol. E92-C, no. 3, pp. 352-355, March 2009, doi: 10.1587/transele.E92.C.352.
Abstract: In memory design, the issue is smaller size and low power. Most power used in the ROM is consumed in line capacitance such as address lines, word lines, bit lines, and decoder. This paper presents ROM design of a novel HG (Half Grouping) compression method so as to reduce the parasitic capacitance of bit lines and the area of the row decoder for power consumption and chip area reduction. ROM design result of 512 point FFT block shows that the proposed method reduces 40.6% area, 42.12% power, and 37.82% transistor number respectively in comparison with the conventional method. The designed ROM with proposed method is implemented in a 0.35 µm CMOS process. It consumes 5.8 mW at 100 MHz with a single 3.3 V power supply.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E92.C.352/_p

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@ARTICLE{e92-c_3_352,
author={Ki-Sang JUNG, Kang-Jik KIM, Young-Eun KIM, Jin-Gyun CHUNG, Ki-Hyun PYUN, Jong-Yeol LEE, Hang-Geun JEONG, Seong-Ik CHO, },
journal={IEICE TRANSACTIONS on Electronics},
title={The ROM Design with Half Grouping Compression Method for Chip Area and Power Consumption Reduction},
year={2009},
volume={E92-C},
number={3},
pages={352-355},
abstract={In memory design, the issue is smaller size and low power. Most power used in the ROM is consumed in line capacitance such as address lines, word lines, bit lines, and decoder. This paper presents ROM design of a novel HG (Half Grouping) compression method so as to reduce the parasitic capacitance of bit lines and the area of the row decoder for power consumption and chip area reduction. ROM design result of 512 point FFT block shows that the proposed method reduces 40.6% area, 42.12% power, and 37.82% transistor number respectively in comparison with the conventional method. The designed ROM with proposed method is implemented in a 0.35 µm CMOS process. It consumes 5.8 mW at 100 MHz with a single 3.3 V power supply.},
keywords={},
doi={10.1587/transele.E92.C.352},
ISSN={1745-1353},
month={March},}

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TY - JOUR
TI - The ROM Design with Half Grouping Compression Method for Chip Area and Power Consumption Reduction
T2 - IEICE TRANSACTIONS on Electronics
SP - 352
EP - 355
AU - Ki-Sang JUNG
AU - Kang-Jik KIM
AU - Young-Eun KIM
AU - Jin-Gyun CHUNG
AU - Ki-Hyun PYUN
AU - Jong-Yeol LEE
AU - Hang-Geun JEONG
AU - Seong-Ik CHO
PY - 2009
DO - 10.1587/transele.E92.C.352
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E92-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 2009
AB - In memory design, the issue is smaller size and low power. Most power used in the ROM is consumed in line capacitance such as address lines, word lines, bit lines, and decoder. This paper presents ROM design of a novel HG (Half Grouping) compression method so as to reduce the parasitic capacitance of bit lines and the area of the row decoder for power consumption and chip area reduction. ROM design result of 512 point FFT block shows that the proposed method reduces 40.6% area, 42.12% power, and 37.82% transistor number respectively in comparison with the conventional method. The designed ROM with proposed method is implemented in a 0.35 µm CMOS process. It consumes 5.8 mW at 100 MHz with a single 3.3 V power supply.
ER -