IEICE TRANSACTIONS on Electronics
An Asynchronous FPGA Based on LEDR/4-Phase-Dual-Rail Hybrid Architecture
Summary :
This paper presents an asynchronous FPGA that combines 4-phase dual-rail encoding and LEDR (Level-Encoded Dual-Rail) encoding. 4-phase dual-rail encoding is employed to achieve small area and low power for function units, while LEDR encoding is employed to achieve high throughput and low power for the data transfer using programmable interconnection resources. Area-efficient protocol converters and their control circuits are also proposed in transistor-level implementation. The proposed FPGA is designed using the e-Shuttle 65nm CMOS process. Compared to the 4-phase-dual-rail-based FPGA, the throughput is increased by 69% with almost the same transistor count. Compared to the LEDR-based FPGA, the transistor count is reduced by 47% with almost the same throughput. In terms of power consumption, the proposed FPGA achieves the lowest power compared to the 4-phase-dual-rail-based and the LEDR-based FPGAs. Compared to the synchronous FPGA, the proposed FPGA has lower power consumption when the workload is below 35%.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E93-C No.8 pp.1338-1348
- Publication Date
- 2010/08/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E93.C.1338
- Type of Manuscript
- PAPER
- Category
- Electronic Circuits
Authors
Keyword
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Shota ISHIHARA, Yoshiya KOMATSU, Masanori HARIYAMA, Michitaka KAMEYAMA, "An Asynchronous FPGA Based on LEDR/4-Phase-Dual-Rail Hybrid Architecture" in IEICE TRANSACTIONS on Electronics,
vol. E93-C, no. 8, pp. 1338-1348, August 2010, doi: 10.1587/transele.E93.C.1338.
Abstract: This paper presents an asynchronous FPGA that combines 4-phase dual-rail encoding and LEDR (Level-Encoded Dual-Rail) encoding. 4-phase dual-rail encoding is employed to achieve small area and low power for function units, while LEDR encoding is employed to achieve high throughput and low power for the data transfer using programmable interconnection resources. Area-efficient protocol converters and their control circuits are also proposed in transistor-level implementation. The proposed FPGA is designed using the e-Shuttle 65nm CMOS process. Compared to the 4-phase-dual-rail-based FPGA, the throughput is increased by 69% with almost the same transistor count. Compared to the LEDR-based FPGA, the transistor count is reduced by 47% with almost the same throughput. In terms of power consumption, the proposed FPGA achieves the lowest power compared to the 4-phase-dual-rail-based and the LEDR-based FPGAs. Compared to the synchronous FPGA, the proposed FPGA has lower power consumption when the workload is below 35%.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E93.C.1338/_p
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@ARTICLE{e93-c_8_1338,
author={Shota ISHIHARA, Yoshiya KOMATSU, Masanori HARIYAMA, Michitaka KAMEYAMA, },
journal={IEICE TRANSACTIONS on Electronics},
title={An Asynchronous FPGA Based on LEDR/4-Phase-Dual-Rail Hybrid Architecture},
year={2010},
volume={E93-C},
number={8},
pages={1338-1348},
abstract={This paper presents an asynchronous FPGA that combines 4-phase dual-rail encoding and LEDR (Level-Encoded Dual-Rail) encoding. 4-phase dual-rail encoding is employed to achieve small area and low power for function units, while LEDR encoding is employed to achieve high throughput and low power for the data transfer using programmable interconnection resources. Area-efficient protocol converters and their control circuits are also proposed in transistor-level implementation. The proposed FPGA is designed using the e-Shuttle 65nm CMOS process. Compared to the 4-phase-dual-rail-based FPGA, the throughput is increased by 69% with almost the same transistor count. Compared to the LEDR-based FPGA, the transistor count is reduced by 47% with almost the same throughput. In terms of power consumption, the proposed FPGA achieves the lowest power compared to the 4-phase-dual-rail-based and the LEDR-based FPGAs. Compared to the synchronous FPGA, the proposed FPGA has lower power consumption when the workload is below 35%.},
keywords={},
doi={10.1587/transele.E93.C.1338},
ISSN={1745-1353},
month={August},}
Copy
TY - JOUR
TI - An Asynchronous FPGA Based on LEDR/4-Phase-Dual-Rail Hybrid Architecture
T2 - IEICE TRANSACTIONS on Electronics
SP - 1338
EP - 1348
AU - Shota ISHIHARA
AU - Yoshiya KOMATSU
AU - Masanori HARIYAMA
AU - Michitaka KAMEYAMA
PY - 2010
DO - 10.1587/transele.E93.C.1338
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E93-C
IS - 8
JA - IEICE TRANSACTIONS on Electronics
Y1 - August 2010
AB - This paper presents an asynchronous FPGA that combines 4-phase dual-rail encoding and LEDR (Level-Encoded Dual-Rail) encoding. 4-phase dual-rail encoding is employed to achieve small area and low power for function units, while LEDR encoding is employed to achieve high throughput and low power for the data transfer using programmable interconnection resources. Area-efficient protocol converters and their control circuits are also proposed in transistor-level implementation. The proposed FPGA is designed using the e-Shuttle 65nm CMOS process. Compared to the 4-phase-dual-rail-based FPGA, the throughput is increased by 69% with almost the same transistor count. Compared to the LEDR-based FPGA, the transistor count is reduced by 47% with almost the same throughput. In terms of power consumption, the proposed FPGA achieves the lowest power compared to the 4-phase-dual-rail-based and the LEDR-based FPGAs. Compared to the synchronous FPGA, the proposed FPGA has lower power consumption when the workload is below 35%.
ER -
English
